74HC_HCT20 All information provided in this document is subject to legal disclaimers. © NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet Rev. 4 — 18 November 2015 6 of 15
NXP Semiconductors
74HC20; 74HCT20
Dual 4-input NAND gate
10. Dynamic characteristics
[1] t
pd
is the same as t
PHL
and t
PLH
.
[2] t
t
is the same as t
THL
and t
TLH
.
[3] C
PD
is used to determine the dynamic power dissipation (P
D
in W):
P
D
=C
PD
V
CC
2
f
i
N+ (C
L
V
CC
2
f
o
) where:
f
i
= input frequency in MHz;
f
o
= output frequency in MHz;
C
L
= output load capacitance in pF;
V
CC
= supply voltage in V;
N = number of inputs switching;
(C
L
V
CC
2
f
o
) = sum of outputs.
Table 7. Dynamic characteristics
GND = 0 V; C
L
= 50 pF; for test circuit see Figure 8.
Symbol Parameter Conditions 25 C 40 C to +125 C Unit
Min Typ Max Max
(85 C)
Max
(125 C)
74HC20
t
pd
propagation delay nA, nB, nC or nD to nY;
see Figure 7
[1]
V
CC
= 2.0 V - 28 90 115 135 ns
V
CC
= 4.5 V - 10 18 23 27 ns
V
CC
= 6.0 V - 8 15 20 23 ns
V
CC
=5.0V; C
L
=15pF - 8 - - - ns
t
t
transition time see Figure 7
[2]
V
CC
= 2.0 V - 19 75 95 110 ns
V
CC
= 4.5 V - 7 15 19 22 ns
V
CC
= 6.0 V - 6 13 16 19 ns
C
PD
power dissipation
capacitance
per package; V
I
=GNDtoV
CC
[3]
-22- - -pF
74HCT20
t
pd
propagation delay nA, nB, nC or nD to nY;
see Figure 7
[1]
V
CC
= 4.5 V - 16 28 35 42 ns
V
CC
= 5.0 V; C
L
=15pF - 13 - - - ns
t
t
transition time V
CC
= 4.5 V; see Figure 7
[2]
- 7 15 19 22 ns
C
PD
power dissipation
capacitance
per package;
V
I
=GNDtoV
CC
1.5 V
[3]
-17- - -pF
