DAC08 Data Sheet
Rev. D | Page 12 of 21
00268-C-028
APPROX
5k
1V
I
REF
(+) 2mA
39k
10k
POT
LOW T.C.
4.5k
V
REF
10V
14
15
Figure 27. Recommended Full-Scale Adjustment Circuit
00268-C-029
R
REF
I
O
I
O
R15
–V
REF
I
FS
–V
REF
R
REF
NOTE
R
REF
SETS I
FS
; R15 IS FOR
BIAS CURRENT CANCELLATION.
14
15
4
2
Figure 28. Basic Negative Reference Operation
00268-C-030
E
O
*OR ADR01
4
2
6
5
10k
+15V –15V
–15V
+15V
5.0k
15V
MSB
B1
B2 B3
B4 B5 B6 B7
LSB
B8
5.000k
5.0k
POS. FULL RANGE
ZERO SCALE
NEG. FULL SCALE +1LSB
NEG. FULL SCALE
B1
1
1
0
0
B2
1
0
0
0
B3
1
0
0
0
B4
1
0
0
0
B5
1
0
0
0
B6
1
0
0
0
B7
1
0
0
0
B8
1
0
1
0
E
O
+4.960
0.000
–4.960
–5.000
10V
REF01*
V
O
–V
4
2
I
O
I
O
V+
C
C
V
LC
AD8671
Figure 29. Offset Binary Operation
00268-C-031
I
O
R
L
I
O
E
O
0 TO –
I
FR
×
R
L
I
FR
= I
REF
255
256
4
2
AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT INVERTING INPUT OF OP AMP TO I
O
(PIN 2): CONNECT I
O
(PIN 4)
TO GROUND.
Figure 30. Positive Low Impedance Output Operation
00268-C-032
I
O
R
L
I
O
E
O
0 TO –I
FR
×
R
L
I
FR
= I
REF
255
256
4
2
AD8671
FOR COMPLEMENTARY OUTPUT (OPERATION AS A NEGATIVE LOGIC DAC).
CONNECT NONINVERTING INPUT OF OP AMP TO
I
O
(PIN 2): CONNECT I
O
(PIN 4)
TO GROUND.
Figure 31. Negative Low Impedance Output Operation
Data Sheet DAC08
Rev. D | Page 13 of 21
00268-C-033
1
TTL, DTL,
V
T
H
= 1.4V
15V
9.1k
6.2k
0.1
µ
F
V
LC
13k
39k
ECL
"A"
3k
TO PIN 1
V
LC
6.2k
5.2V
20k
20k
V+
"A"
3k
TO PIN 1
V
LC
R3
400
µ
A
C
MO
S,
H
T
L
,
N
MO
S
TEMPERATURE COMPENSATING V
LC
CIRCUITS
V
TH
= V
LC
1.4V
15V CMOS
V
TH
= 7.6V
V
LC
2N3904
2N3904
2N3904
2N3904
Figure 32. Interfacing with Various Logic Families
DAC08 Data Sheet
Rev. D | Page 14 of 21
APPLICATION INFORMATION
REFERENCE AMPLIFIER SETUP
The DAC08 is a multiplying D/A converter in which the output
current is the product of a digital number and the input reference
current. The reference current may be fixed or may vary from
nearly zero to 4.0 mA. The full-scale output current is a linear
function of the reference current and is given by
REFFR
II
256
255
where I
REF
= I
14
In positive reference applications, an external positive reference
voltage forces current through R14 into the V
REF(+)
terminal (Pin 14)
of the reference amplifier. Alternatively, a negative reference may be
applied to V
REF(–)
at Pin 15; reference current flows from ground
through R14 into V
REF(+)
as in the positive reference case. This
negative reference connection has the advantage of a very high
impedance presented at Pin 15. The voltage at Pin 14 is equal to
and tracks the voltage at Pin 15 due to the high gain of the internal
reference amplifier. R15 (nominally equal to R14) cancels bias
current errors; R15 may be eliminated with only a minor
increase in error.
Bipolar references may be accommodated by offsetting V
REF
or
Pin 15. The negative common-mode range of the reference
amplifier is given by V
CM
– = V− plus (I
REF
× 1 kΩ) plus 2.5 V.
The positive common-mode range is V+ less 1.5 V.
When a dc reference is used, a reference bypass capacitor is
recommended. A 5.0 V TTL logic supply is not recommended
as a reference. If a regulated power supply is used as a reference,
R14 must be split into two resistors with the junction bypassed
to ground with a 0.1 μF capacitor.
For most applications, the tight relationship between I
REF
and I
FS
eliminates the need for trimming I
REF.
If required, full-scale
trimming can be accomplished by adjusting the value of R14, or
by using a potentiometer for R14. An improved method of full-
scale trimming that eliminates potentiometer T.C. effects is shown
in the recommended full-scale adjustment circuit (Figure 27).
Using lower values of reference current reduces negative power
supply current and increases reference amplifier negative common-
mode range. The recommended range for operation with a dc
reference current is 0.2 mA to 4.0 mA.
REFERENCE AMPLIFIER COMPENSATION FOR
MULTIPLYING APPLICATIONS
AC reference applications require the reference amplifier to be
compensated using a capacitor from Pin 16 to V−. e value of
this capacitor depends on the impedance presented to Pin 14;
for R14 values of 1.0 kΩ, 2.5 kΩ, and 5.0 kΩ, minimum values
of C
C
are 15 pF, 37 pF, and 75 pF. Larger values of R14 require
proportionately increased values of C
C
for proper phase margin,
so the ratio of C
C
(pF) to R14 (kΩ) = 15.
For fastest response to a pulse, low values of R14 enabling small
C
C
values must be used. If Pin 14 is driven by a high impedance
such as a transistor current source, none of the preceding values
suffice, and the amplifier must be heavily compensated, which
decreases overall bandwidth and slew rate. For R14 = 1 kΩ and
C
C
= 15 pF, the reference amplifier slews at 4 mA/μs, enabling a
transition from I
REF
= 0 to I
REF
= 2 mA in 500 ns.
Operation with pulse inputs to the reference amplifier can be
accommodated by an alternate compensation scheme. This
technique provides lowest full-scale transition times. An internal
clamp allows quick recovery of the reference amplifier from a
cutoff (I
REF
= 0) condition. Full-scale transition (0 mA to 2 mA)
occurs in 120 ns when the equivalent impedance at Pin 14 is 200 Ω
and C
C
= 0. This yields a reference slew rate of 16 mA/μs, which
is relatively independent of the R
IN
and V
IN
values.
LOGIC INPUTS
The DAC08 design incorporates a unique logic input circuit that
enables direct interface to all popular logic families and provides
maximum noise immunity. This feature is made possible by the
large input swing capability, 2 μA logic input current, and
completely adjustable logic threshold voltage. For V− = −15 V, the
logic inputs may swing between −10 V and +18 V. This enables
direct interface with 15 V CMOS logic, even when the DAC08
is powered from a 5 V supply. Minimum input logic swing and
minimum logic threshold voltage are given by
V− + (I
REF
× 1 kΩ) + 2.5 V
The logic threshold may be adjusted over a wide range by
placing an appropriate voltage at the logic threshold control pin
(Pin 1, V
LC
). Figure 16 shows the relationship between V
LC
and
V
TH
over the temperature range, with V
TH
nominally 1.4 above
V
LC
. For TTL and DTL interface, simply ground Pin 1. When
interfacing ECL, an I
REF
= 1 mA is recommended. For interfacing
other logic families, see Figure 32. For general set-up of the logic
control circuit, note that Pin 1 sources 100 μA typical; external
circuitry must be designed to accommodate this current.
Fastest settling times are obtained when Pin 1 sees a low
impedance. If Pin 1 is connected to a 1 kΩ divider, for example,
it must be bypassed to ground by a 0.01 μF capacitor.
ANALOG OUTPUT CURRENTS
Both true and complemented output sink currents are provided
where I
O
+
I
O
= I
FS
. Current appears at the true (I
O
) output when
a 1 (logic high) is applied to each logic input. As the binary count
increases, the sink current at Pin 4 increases proportionally, in
the fashion of a positive logic DAC. When a 0 is applied to any
input bit, that current is turned off at Pin 4 and turned on at Pin 2.
A decreasing logic count increases
I
O
as in a negative or inverted
logic DAC. Both outputs may be used simultaneously.

DAC08CSZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC IC 8-BIT HIGH-Spd MULTIPLY
Lifecycle:
New from this manufacturer.
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