LTC4217
13
4217fg
For more information www.linear.com/LTC4217
Once the PG comparator is high the GATE pin voltage is
monitored with respect to the OUT pin. Once the GATE
minus OUT voltage exceeds 4.2V the PG pin goes high.
This indicates to the system that it is safe to load the OUT
pin while the MOSFET is completely turned “on”. The PG
pin goes low when the GATE is commanded off (using
the UV, OV or SENSE pins) or when the PG comparator
drives low.
12V Fixed Version
In the LTC4217-12 the UV, OV and FB pins are driven by
internal dividers which may need to be filtered to prevent
false faults. By placing a bypass capacitor on these pins
the faults are delayed by the RC time constant. Use the
R
IN
value from the electrical characteristics table for this
calculation.
In cases where the fixed thresholds need a slight adjust
-
ment, placing a resistor from the UV or OV pins to V
DD
or GND will adjust the threshold up or down. Likewise
placing a resistor between FB pin to OUT or GND adjusts
the threshold. Again use the R
IN
value from the electrical
characteristics table for this calculation.
An example in Figure 5 raises the UV turn-on voltage from
9.88V to 10.5V. Increasing the UV level requires adding a
resistor between UV and ground. The resistor, R
SHUNT1
, can
be calculated using electrical table parameters as follows:
R
SHUNT1
=
IN
( )
OLD
V
NEW
– V
OLD
( )
=
18k • 9.88V
10.5V – 9.88V
( )
= 287k
applicaTions inForMaTion
or ADC. The voltage compliance for the I
MON
pin is from
0V to INTV
CC
– 0.7V.
A microcontroller with a built-in comparator can build a
simple integrating single-slope ADC by resetting a capaci
-
tor that is charged with this current. When the capacitor
voltage trips the comparator and the capacitor is reset, a
timer is started. The time between resets will indicate the
MOSFET current.
Monitor OV and UV Faults
Protecting the load from an overvoltage condition is the
main function of the OV pin. In the LTC4217-12, an in
-
ternal resistive divider (driving the OV pin) connects to a
comparator to turn off the MOSFET when the V
DD
voltage
exceeds 15.05V. If the V
DD
pin subsequently falls back
below 14.8V, the switch will be allowed to turn on im-
mediately. In the LTC4217 the OV pin threshold is 1.235V
when rising, and
1.215V
when falling out of overvoltage.
The UV pin functions as an undervoltage protection pin or
as an “ON” pin. In the LTC4217-12 the MOSFET turns off
when V
DD
falls below 9.23V. If the V
DD
pin subsequently
rises above 9.88V for 100ms, the switch will be allowed
to turn on again. The LTC4217 UV turn-on/off thresholds
are 1.235V (rising) and 1.115V (falling).
In the cases of an undervoltage or overvoltage the MOSFET
turns off and there is indication on the PG status pin. When
the overvoltage is removed the MOSFET’s gate ramps up
immediately at the rate determined by the INRUSH block.
Power Good Indication
In addition to setting the foldback current limit threshold,
the FB pin is used to determine a power good condition.
The LTC4217-12 uses an internal resistive divider on the
OUT pin to drive the FB pin. The PG comparator indicates
logic high when OUT pin rises above 10.5V. If the OUT pin
subsequently falls below 10.3V the comparator toggles
low. On the LTC4217 the PG comparator drives high when
the FB pin rises above 1.235V and low when falls below
1.215V.
Figure 5. Adjusting LTC4217-12 Thresholds
4217 F05
LTC4217-12
R
SHUNT1
R
SHUNT2
V
DD
OV
UV
