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HI5728EVAL1

P1-P3P4-P6P7-P9P10-P12
3-7
Appendix C Circuit Board Layout
FIGURE 3. PRIMARY SIDE
FIGURE 4. GROUND LAYER (2)
Application Note 9827
3-8
FIGURE 5. POWER LAYER (3)
FIGURE 6. SECONDARY SIDE
Appendix C Circuit Board Layout (Continued)
Application Note 9827
3-9
SMA8
ICLK
SMA9
QCLK
C13
P1-77
CLK
R49
50Ω
R55
50Ω
R21
50Ω
R28
200Ω
R29
200Ω
R50
0Ω
R53
0Ω
PIN 43
PIN 42
ICLK
QCLK
VME CONNECTOR
DGND1
C14
0.1µF
C13
10µF
DVDD1
+
FB2
10µH
AGND1
C9
0.1µF
C8
10µF
AVDD1
+
FB1
10µH
TO DIGITAL POWER PLANE
TO DIGITAL GROUND PLANE
TO ANALOG POWER PLANE
TO ANALOG GROUND PLANE
= ANALOG GROUND (AGND1)
= DIGITAL GROUND (DGND1)
OF THE HI5728
PINS 9, 29, 40, 45
OF THE HI5728
PINS 10, 28, 41, 44
OF THE HI5728
PINS 12, 26
OF THE HI5728
PINS 13,18, 19, 25
SMA10
SMA11
E10
E11
R58
0Ω
QD9
ID9
R60
0Ω
QD8
ID8
R59
0Ω
QD7
ID7
R54
0Ω
QD6
ID6
R62
0Ω
QD5
ID5
R65
0Ω
QD4
ID4
R66
0Ω
QD3
ID3
R64
0Ω
QD2
ID2
R63
0Ω
QD1
ID1
R67
0Ω
QD0
ID0
C1
0.1µF
C15
0.1µF
C6
0.1µF
C5
0.1µF
PIN 9 PIN 29 PIN 40 PIN 45
C3 0.1µF C12 0.1µF
PIN 12 PIN 26
C16
10µF
+
V
DD1
Power Supply Input Circuit
Extra SMAs (See ‘Voltage Reference’ text for
explanation.)
Digital Input Additional Connections
Ground Symbol Definition
Extra Power Supply Input
Located near Output Proto Area
(Used if additional circuity is added in the proto area)
Power Supply Decoupling
DV
DD
Power Decoupling Capacitors
AV
DD
Power Decoupling Capacitors
Clock Input Circuit (See ‘Clock
Inputs’ Text.)
NOTE: DV
DD
and AV
DD
can be tied together for single supply operation.
AGND1 and DGND1 are tied together at a single point. See text for further
explanation.
Application Note 9827
P1-P3P4-P6P7-P9P10-P12

HI5728EVAL1

Mfr. #:
Buy HI5728EVAL1
Manufacturer:
Renesas / Intersil
Description:
Data Conversion IC Development Tools HI5728EVAL PLA TFORM FOR TQFP
Lifecycle:
New from this manufacturer.
Delivery:
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