OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

ADV3205JSTZ

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21
Data Sheet ADV3205
Rev. 0 | Page 9 of 20
TRUTH TABLE AND LOGIC DIAGRAM
Table 8. Operation Truth Table
1
CE
UPDATE
CLK DATA IN DATA OUT
RESET
SER
/PAR
Operation/Comment
1 X X X X X X No change in logic.
0 1
↓
2
Data
i
Data
i-80
1 0
The data on the serial DATA IN line is loaded into the serial
register. The first bit clocked into the serial register appears at
DATA OUT 80 clocks later.
0 1
↓
3
D0 ... D4,
A0 ... A3
Not
applicable
in parallel
mode
1 1
The data on the parallel data lines, D0 to D4, are loaded into
the 80-bit serial shift register location addressed by A0 to A3.
0 0 X X X 1 X
Data in the 80-bit shift register transfers into the parallel
latches that control the switch array. Latches are transparent.
X X X X X 0 X
Asynchronous operation. All outputs are disabled. Remainder
of logic is unchanged.
1
X = don’t care, 0 = logic low, 1 = logic high, and ↓ = falling edge triggered.
2
↓ = falling edge triggered.
3
↓ = low level triggered.
D
CLK
Q
4 TO 16 DECODER
A0
A1
A2
CLK
16
256
DATA IN
(SERIAL)
(OUTPUT
ENABLE)
SER/PAR
CE
UPDATE
OUT00 EN
DATA
OUT
PARALLEL
DATA
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D1
D2
D3
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
D
Q
CLK
OUT01 EN
OUT02 EN
OUT03 EN
OUT04 EN
OUT05 EN
OUT06 EN
OUT07 EN
D
LE
QCLR
OUT15
EN
OUTPUT ENABLE
SWITCH MATRIX
S
D1
Q
D0
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
S
D1
Q
D0
D
Q
CLK
S
D1
Q
D0
D4
DECODE
D
LE
QCLR
OUT00
EN
D
LE
OUT00
B0
Q
D
LE
Q
OUT00
B1
D
LE
Q
OUT00
B2
D
LE
Q
OUT00
B3
D
LE
OUT01
B0
Q
D
LE
QCLR
OUT14
EN
D
LE
OUT15
B0
Q
D
LE
OUT15
B1
Q
D
LE
OUT15
B2
Q
D
Q
CLK
S
D1
Q
D0
S
D1
Q
D0
D
LE
OUT15
B3
Q
S
D1
Q
D0
OUT08 EN
OUT09 EN
OUT10 EN
OUT11 EN
OUT12 EN
OUT13 EN
OUT14 EN
OUT15 EN
A3
OUTPUT
ADDRESS
RESET
(OUTPUT ENABLE)
10342-005
Figure 6. Logic Diagram
ADV3205 Data Sheet
Rev. 0 | Page 10 of 20
TYPICAL PERFORMANCE CHARACTERISTICS
T
A
= 25°C, V
S
= ±5 V, R
L
= 150 , unless otherwise noted.
FREQUENCY (MHz)
–6
–3
0
GAIN (dB)
3
0.01 0.1 1 10 100
10342-012
0.1 1 10 100
FREQUENCY (MHz)
–6
–3
0
GAIN (dB)
3
10342-015
Figure 7. Small Signal Bandwidth, V
OUT
= 200 mV p-p
Figure 10. Large Signal Bandwidth, V
OUT
= 2 V p-p
FREQUENCY (MHz)
–0.3
–0.1
0.1
GAIN FLATNESS (dB)
0.3
–0.2
0
0.2
0.1 1 10 100
10342-016
FREQUENCY (MHz)
–0.3
–0.1
0.1
GAIN FLATNESS (dB)
0.3
–0.2
0
0.2
0.1 1 10 100
10342-013
Figure 11. Large Signal Gain Flatness, V
OUT
= 2 V p-p
Figure 8. Small Signal Gain Flatness, V
OUT
= 200 mV p-p
0.001 0.01 0.1 1 10010
FREQUENCY (MHz)
–110
–100
–80
–60
CROSSTALK (dB)
–
50
–90
–70
10342-017
SECOND HARMONIC
THIRD HARMONIC
FREQUENCY (MHz)
–100
–80
–60
CROSSTALK (dB)
–
40
–90
–70
–50
0.1 1 10 100
10342-014
ALL HOSTILE
ADJACENT
Figure 9. Crosstalk vs. Frequency, V
OUT
= 2 V p-p
Figure 12. Distortion vs. Frequency, V
OUT
= 2 V p-p
Data Sheet ADV3205
Rev. 0 | Page 11 of 20
FREQUENCY (MHz)
–90
–70
–30
PSRR (dB)
0
–80
–50
–10
–40
–60
–20
0.01 0.1 1 10
10342-018
+PSRR
–PSRR
Figure 13. PSRR vs. Frequency
FREQUENCY (MHz)
IMPEDANCE (Ω)
1k
100
10
1
0.1
0.1 1 10 100 1k
10342-019
Figure 14. Enabled Output Impedance vs. Frequency
FREQUENCY (MHz)
–120
–80
–40
OFF ISOLATION (dB)
0
–100
–60
–20
0.1 1 10 100
10342-020
Figure 15. Off Isolation vs. Frequency, V
OUT
= 2 V p-p
FREQUENCY (Hz)
0
40
120
NOISE (nV
√
Hz)
160
20
80
100
60
140
10 100 1k 10k 1M100k 10M
10342-021
Figure 16. Noise vs. Frequency
FREQUENCY (MHz)
IMPEDANCE (Ω)
10k
1k
100
10
1
0.1 1 10 100 1k
10342-022
Figure 17. Disabled Output Impedance vs. Frequency
051052025
5ns/DIV
0.1%/DI
V
30 35 40 45 50
OUTPUT
2
– INPUT
OUTPUT
INPUT
10342-023
Figure 18. Settling Time to 0.1%, 2 V Output Step
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21

ADV3205JSTZ

Mfr. #:
Buy ADV3205JSTZ
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 60MHz 16 x 16 Buffered
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet