Data Sheet ADV3205
Rev. 0 | Page 15 of 20
APPLICATIONS INFORMATION
The ADV3205 has two options for changing the programming of
the crosspoint matrix. In the first option, a serial word of 80 bits can
be provided that updates the entire matrix in one serial operation.
The second option allows for changing the programming of a
single output via a parallel interface. The serial option requires
fewer signals but more time (clock cycles) for changing the
programming, whereas the parallel programming technique
requires more signals, but can change a single output at a time,
and requires fewer clock cycles to complete programming.
SERIAL PROGRAMMING
The serial programming mode uses the device pins:
CE
, CLK,
DATA IN,
UPDATE
, and
SER
/PAR. The first step is to assert a
low on
SER
/PAR to enable the serial programming mode.
CE
for the chip must be low to allow data to be clocked into the
device. The
CE
signal can be used to address an individual
device when devices are connected in parallel.
The
UPDATE
signal should be high during the time that data is
shifted into the serial port of the device. Although the data still
shifts in when
UPDATE
is low, the transparent, asynchronous
latches allow the shifting data to reach the matrix. This causes
the matrix to try to update to every intermediate state as defined by
the shifting data.
The data at DATA IN is clocked in at every down edge of CLK. A
total of 80 bits must be shifted into the shift register via the DATA
IN input to complete the programming. For each of the 16 outputs,
there are four bits (D0 to D3) that determine the source of its
input followed by one bit (D4) that determines the enabled state
of the output. If D4 is low (output disabled), the four associated
bits (D0 to D3) do not matter because no input is switched to
that output.
The most significant output address data is shifted into the shift
register first, following in sequence until the least significant
output address data is shifted in. At this point
UPDATE
can be
taken low, which causes the programming of the device according
to the data that was just shifted in. The
UPDATE
registers are
asynchronous, and when
UPDATE
is low (and
CE
is low), the
registers are transparent.
When more than one ADV3205 device is serially programmed in a
system, the DATA OUT signal from one device can be connected
to the DATA IN of the next device to form a serial chain. Connect
all of the CLK,
CE
,
UPDATE
, and
SER
/PAR pins in parallel and
operate them as previously described. The serial data is input to
the DATA IN pin of the first device of the chain, and it ripples
through to the last. Therefore, the data for the last device in the
chain should come at the beginning of the programming sequence.
The length of the programming sequence is 80 bits times the
number of devices in the chain.
PARALLEL PROGRAMMING
When using the parallel programming mode, it is not necessary
to reprogram the entire device when making changes to the matrix.
In fact, parallel programming allows for the modification of a
single output at a time. Because this takes only one CLK/
UPDATE
cycle, significant time savings can be realized by using parallel
programming.
One important consideration in using parallel programming is
that the
RESET
signal does not reset all registers in the .
When taken low, the
ADV3205
RESET
signal only sets each output to the
disabled state. This is helpful during power-up to ensure that
two parallel outputs are not active at the same time.
After initial power-up, the internal registers in the device generally
contain random data, even though the
RESET
signal has been
asserted. If parallel programming is used to program one output,
that output is properly programmed but the rest of the device
has a random program state depending on the internal register
content at power-up. Therefore, when using parallel programming,
it is essential that all outputs be programmed to a desired state
after power-up. This ensures that the programming matrix is
always in a known state. From then on, parallel programming
can be used to modify a single output at a time.
In similar fashion, if both
CE
and
UPDATE
are taken low after
initial power-up, the random power-up data in the shift register is
programmed into the matrix. Therefore, to prevent the crosspoint
from being programmed into an unknown state, do not apply
low logic levels to both
CE
and
UPDATE
after power is initially
applied. Programming the full shift register one time to a desired
state, by either serial or parallel programming after initial power-up,
eliminates the possibility of programming the matrix to an
unknown state.
To change the outputs programming via parallel programming,
take
SER
/PAR and
UPDATE
high and take
CE
low. The CLK
signal should be in the high state. Put the 4-bit address of the
output to be programmed on the A0 to A3 pins. The first four
data bits (D0 to D3) should contain the information that identifies
the input that is programmed to the output that is addressed.
The fifth data bit (D4) determines the enabled state of the output. If
D4 is low (output disabled), the data on D0 to D3 does not matter.
After the desired address and data signals are established, they
can be latched into the shift register by a high-to-low transition
of the CLK signal. The matrix is not programmed, however, until
the
UPDATE
signal is taken low. It is thus possible to latch in
new data for several or all of the outputs first via successive
negative transitions of CLK while
UPDATE
is held high and then
have all of the new data take effect when
UPDATE
goes low.
Use this technique when programming the device for the first
time after power-up when using parallel programming.
ADV3205 Data Sheet
Rev. 0 | Page 16 of 20
POWER-ON RESET
When powering up the ADV3205, it is usually desirable to have
the outputs start up in the disabled state. The
RESET
pin, when
taken low, causes all outputs to be in the disabled state. However,
the
RESET
signal does not reset all registers in the .
This is important when operating in parallel programming mode.
Refer to the section for information
about programming internal registers after power-up. Serial
programming programs the entire matrix each time; therefore,
no special considerations apply.
ADV3205
Parallel Programming
Because the data in the shift register is random after power-up,
do not use it to program the matrix or the matrix can enter
unknown states. To prevent this, do not apply logic low signals
to both
CE
and
UPDATE
initially after power-up. First, load the
shift register with the desired data, and then take
UPDATE
low
to program the device.
The
RESET
pin has a 20 kΩ pull-up resistor to DV
CC
that can be
used to create a simple power-up reset circuit. A capacitor from
RESET
to ground holds
RESET
low for some time while the rest
of the device stabilizes. The low condition causes all outputs to
be disabled. The capacitor then charges through the pull-up resistor
to the high state, thus allowing full programming capability of
the device.
MANAGING VIDEO SIGNALS
Video signals often use controlled impedance transmission lines
that are terminated in their characteristic impedance. Although this
is not always the case, there are some considerations when using
the ADV3205 to route video signals with controlled impedance
transmission lines. Figure 29 shows a schematic of an input
and output treatment of a typical video channel.
75
75
75
75
TRANSMISSION
LINE
TYPICAL
OUTPUT
+5
V
ADV3205
G = 2
–5V
TYPICAL
INPUT
75
VIDEO
SOURCE
10342-031
Figure 29. Video Signal Circuit
Video signals most often use 75  transmission lines that need
to be terminated with this value of resistance at each end. When
such a source is delivered to one of the ADV3205 inputs, the
high input impedance does not properly terminate these signals.
Therefore, terminate the line with a 75  shunt resistor to
ground. Because video signals are limited in their peak-to-peak
amplitude (typically no more than 1.5 V p-p), there is no need
to attenuate video signals before they pass through the ADV3205.
The ADV3205 outputs are low impedance and do not properly
terminate the source end of a 75  transmission line. In these
cases, insert a series 75  resistor at an output that drives a video
signal. Then terminate the 75  transmission line with 75  at
its far end. This overall termination scheme divides the amplitude
of the ADV3205 output by two. An overall unity-gain channel is
produced because of the channel gain-of-two of the ADV3205.
CREATING LARGER CROSSPOINT ARRAYS
The ADV3205 is a high density building block for creating
crosspoint arrays of dimensions larger than 16 × 16. Various
features, such as output disable and chip enable, are useful for
creating larger arrays.
The first consideration in constructing a larger crosspoint is to
determine the minimum number of devices that are required. The
16 × 16 architecture of the ADV3205 contains 256 points, which is
a factor of 64 greater than a 4 × 1 crosspoint (or multiplexer). The
printed circuit board (PCB) area, power consumption, and design
effort savings are readily apparent when compared to using
these smaller devices.
For a nonblocking crosspoint, the number of points required is
the product of the number of inputs multiplied by the number
of outputs. Nonblocking requires that the programming of a
given input to one or more outputs does not restrict the
availability of that input to be a source for any other outputs.
Some nonblocking crosspoint architectures require more than this
minimum as previously calculated. In addition, there are blocking
architectures that can be constructed with fewer devices than this
minimum. These systems have connectivity available on a statistical
basis that is determined when designing the overall system.
The basic concept in constructing larger crosspoint arrays is to
connect inputs in parallel in a horizontal direction and to wire-OR
the outputs together in the vertical direction. The meaning of
horizontal and vertical can best be understood by looking at a
diagram. Figure 30 illustrates this concept for a 32 × 32 crosspoint
array that uses four ADV3205 devices. Note that the 75 Ω source
terminations are not shown on the outputs, but they are required
when driving the 75 Ω transmission lines.
ADV3205
ADV3205
IN00 TO IN15
IN16 TO IN31
ADV3205
ADV3205
16
16
16
16
75
75
16
16
16
8
16
16
10342-032
Figure 30. 32 × 32 Crosspoint Array Using Four ADV3205 Devices
Data Sheet ADV3205
Rev. 0 | Page 17 of 20
The inputs are individually assigned to each of the 32 inputs of
the two devices, and the shunt 75  terminations are placed at
the end of the transmission lines. The outputs are wire-ORed
together in pairs. Only enable one of the outputs from a wire-
ORed pair at any given time. The device programming software
must be properly written to achieve this.
MULTICHANNEL VIDEO
The good video specifications of the ADV3205 make it an ideal
candidate for creating composite video crosspoint switches. These
switches can be made quite dense by taking advantage of the
high level of integration of the ADV3205 and the fact that
composite video requires only one crosspoint channel per system
video channel. There are, however, other video formats that can
be routed with the ADV3205, requiring more than one crosspoint
channel per video channel.
Some systems use twisted pair wiring to carry video signals.
These systems use differential signals and can lower costs
because they use lower cost cables, connectors, and termination
methods. They also have the ability to lower crosstalk and reject
common-mode signals, which can be important for equipment
that operates in noisy environments, or where common-mode
voltages are present between transmitting and receiving equipment.
In such systems, the video signals are differential; there are positive
and negative (or inverted) versions of the signals. These
complementary signals are transmitted onto each of the two
wires of the twisted pair, yielding a first-order zero common-
mode voltage. At the receive end, the signals are differentially
received and converted back into a single-ended signal.
When switching these differential signals, two channels are
required in the switching element to handle the two differential
signals that make up the video channel. Thus, one differential
video channel is assigned to a pair of crosspoint channels, both
input and output. For a single ADV3205, eight differential video
channels can be assigned to the 16 inputs and 16 outputs. This
effectively forms an 8 × 8 differential crosspoint switch.
Programming such a device requires that the inputs and outputs
be programmed in pairs. This information can be deduced through
inspection of the programming format of the ADV3205 and the
requirements of the system.
There are other analog video formats requiring more than one
analog circuit per video channel. One two-circuit format that is
commonly being used in video systems is S-Video or Y/C Video.
The Y/C Video format carries the brightness (luminance or Y)
portion of the video signal on one channel and the color
(chrominance, chroma, or C) on a second channel.
Because S-Video also uses two separate circuits for one video
channel, creating a crosspoint system requires assigning one
video channel to two crosspoint channels, as in the case of a
differential video system. Aside from the nature of the video
format, other aspects of these two systems are the same.
There are yet other video formats using three channels to carry
the video information. Video cameras produce RGB (red, green,
and blue) directly from the image sensors. RGB is also the usual
format used by computers internally for graphics. RGB can also
be converted to Y, R–Y, and B–Y format, sometimes called YUV
format. These three circuit video standards are referred to as
analog component video.
The analog component video standards require three crosspoint
channels per video channel to handle the switching function. In
a fashion similar to the two circuit video formats, the inputs and
outputs are assigned in groups of three, and the appropriate logic
programming is performed to route the video signals.
CROSSTALK
Many video systems have strict requirements for keeping the
various signals from influencing any of the others in the system.
Crosstalk is the term used to describe the coupling of the signals of
other nearby channels to a given channel.
When there are many signals in proximity in a system, as is the
case in a system that uses the ADV3205, the crosstalk issues can
be quite complex. A good understanding of the nature of crosstalk
and some definition of terms is required to specify a system that
uses one or more ADV3205 devices.
Types of Crosstalk
Crosstalk can be propagated by means of any of three methods.
These fall into the categories of electric field, magnetic field, and
sharing of common impedances. This section explains these effects.
Every conductor can be both a radiator of electric fields and a
receiver of electric fields. The electric field crosstalk mechanism
occurs when the electric field created by the transmitter propagates
across a stray capacitance (for example, free space) and couples
with the receiver and induces a voltage. This voltage is an unwanted
crosstalk signal in any channel that receives it.
Currents flowing in conductors create magnetic fields that circulate
around the currents. These magnetic fields then generate voltages
in any other conductors with whose paths they link. The undesired
induced voltages in these other channels are crosstalk signals.
The channels that crosstalk can be said to have a mutual inductance
that couples signals from one channel to another.
The power supplies, grounds, and other signal return paths of a
multichannel system are generally shared by the various channels.
When a current from one channel flows in one of these paths, a
voltage that is developed across the impedance becomes an input
crosstalk signal for other channels that share the common
impedance.
All these sources of crosstalk are vector quantities; therefore, the
magnitudes cannot simply be added together to obtain the total
crosstalk. In fact, there are conditions where driving additional
circuits in parallel in a given configuration can actually reduce
the crosstalk.

ADV3205JSTZ

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Analog & Digital Crosspoint ICs 60MHz 16 x 16 Buffered
Lifecycle:
New from this manufacturer.
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