OMO ElectronicOMO Electronic
Expand menu
Hello, Sign inMy Account
0 Cart

8701CYLFT

P1-P3P4-P6P7-P9P10-P12P13-P13
Low Skew, ÷1, ÷2
LVCMOS/LVTTL Clock Generator
8701
DATASHEET
8701 REVISION F JANUARY 21, 2015 1 ©2015 Integrated Device Technology, Inc.
GENERAL DESCRIPTION
The 8701 is a low skew, ÷1, ÷2 LVCMOS/LVTTL Clock
Generator . The low impedance LVCMOS outputs are
designed to drive 50Ω series orparallel terminated
transmission lines. The effective fanout can be increased from
20 to 40 by utilizing the ability of the outputs to drive two series
terminated lines.
The divide select inputs, DIV_SELx, control the output
frequency of each bank. The outputs can be utilized in
the ÷1, ÷2 or a combination of ÷1 and ÷2 modes. The
bank enable inputs, BANK_EN0:1, support enabling and
disabling each bank of outputs individually. The master
reset input, nMR/OE, resets the internal frequency dividers and
also controls the active and high impedance states of all outputs.
The 8701 is characterized at 3.3V and mixed
3.3V input supply, and 2.5V output supply operating
modes. Guaranteed bank, output and part-to-part skew
characteristics make the 8701 ideal for those clock
distribution applications demanding well defined
performance and repeatability.
FEATURES
• Twenty LVCMOS outputs, 7Ω typical output impedance
• One LVCMOS/LVTTL clock input
• Maximum output frequency: 250MHz
• Bank enable logic allows unused banks to be disabled
in reduced fanout applications
• Output skew: 250ps (maximum)
• Part-to-part skew: 600ps (maximum)
• Bank skew: 200ps (maximum)
• Multiple frequency skew: 300ps (maximum)
• 3.3V or mixed 3.3V input, 2.5V output operating
supply modes
• 0°C to 70°C ambient operating temperature
• Other divide values available on request
• Available in lead-free RoHS compliant package
BLOCK DIAGRAM PIN ASSIGNMENT
48-Pin LQFP
7mm x 7mm x 1.4mm
Y Package
Top View
LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
8701 DATA SHEET
2 REVISION F 1/21/15
TABLE 1. PIN DESCRIPTIONS
Number Name Type Description
2, 5, 11,
26, 32, 35, 41,
44
V
DDO
Power Output supply pins.
7, 9, 18, 21,
28, 30, 37, 39,
46, 48
GND Power Power supply ground.
16, 20 V
DD
Power Positive supply pins.
25, 27, 29,
31, 33
QA0, QA1, QA2,
QA3, QA4
Output
Bank A outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
34, 36, 38,
40, 42
QB0, QB1, QB2,
QB3, QB4
Output
Bank B outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
43, 45, 47,
1, 3
QC0, QC1, QC2,
QC3, QC4
Output
Bank C outputs.LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
4, 6, 8,
10, 12
QD0, QD1, QD2,
QD3, QD4
Output
Bank D outputs. LVCMOS / LVTTLinterface levels.
7Ω typical output impedance.
22 CLK Input Pulldown LVCMOS / LVTTL clock input.
13 DIV_SELD Input Pullup
Controls frequency division for Bank D outputs.
LVCMOS / LVTTLinterface levels.
14 DIV_SELC Input Pullup
Controls frequency division for Bank C outputs.
LVCMOS / LVTTLinterface levels.
23 DIV_SELB Input Pullup
Controls frequency division for Bank B outputs.
LVCMOS / LVTTLinterface levels.
24 DIV_SELA Input Pullup
Controls frequency division for Bank A outputs.
LVCMOS / LVTTLinterface levels.
17, 19
BANK_EN1,
BANK_EN0
Input Pullup
Enables and disables outputs by banks.
LVCMOS / LVTTLinterface levels.
15 nMR/OE Input Pullup
Master Reset and output enable. When HIGH, output drivers are
enabled. Whe LOW, output drivers are in HiZ and dividers are reset.
LVCMOS / LVTTLinterface levels.
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
REVISION F 1/21/15
8701 DATA SHEET
3 LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
TABLE 2. PIN CHARACTERISTICS
TABLE 3. FUNCTION TABLE
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 4 pF
R
PULLUP
Input Pullup Resistor 51
kΩ
R
PULLDOWN
Input Pulldown Resistor 51
kΩ
C
PD
Power Dissipation Capacitance
(per output)
V
DD
, V
DDO
= 3.465V 15 pF
R
OUT
Output Impedance 7
Ω
Inputs Outputs
nMR/OE BANK_EN1 BANK_EN0 DIV_SELx QA0:QA4 QB0:QB4 QC0:QC4 QD0:QD4 Qx Frequency
0 X X X Hi Z Hi Z Hi Z Hi Z zero
1 0 0 0 Active Hi Z Hi Z Hi Z fIN/2
1 1 0 0 Active Active Hi Z Hi Z fIN/2
1 0 1 0 Active Active Active Hi Z fIN/2
1 1 1 0 Active Active Active Active fIN/2
1 0 0 1 Active Hi Z Hi Z Hi Z fIN
1 1 0 1 Active Active Hi Z Hi Z fIN
1 0 1 1 Active Active Active Hi Z fIN
1 1 1 1 Active Active Active Active fIN
P1-P3P4-P6P7-P9P10-P12P13-P13

8701CYLFT

Mfr. #:
Buy 8701CYLFT
Manufacturer:
IDT
Description:
Clock Generators & Support Products 20 LVCMOS OUT BUFFER/DIVIDER
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet