LOW SKEW, ÷1, ÷2
LVCMOS/LVTTL CLOCK GENERATOR
8701 DATA SHEET
12 REVISION F 1/21/15
Rev Table Page Description of Change Date
B
5A
5B
5
7
8 - 10
Updated notes.
Updated notes.
Updated drawings
10/4/01
C
4B
4D
4
6
11
Revised V
IH
rows from 3.8 Maximum to V
DD
+ 0.3 Maximum.
Revised V
IH
rows from 3.8 Maximum to V
DD
+ 0.3 Maximum.
Added Power Dissipation and Driver Termination notes.
11/28/01
C
12
9
Pin Description Table, revised nMR/OE description.
Updated Output Rise/Fall Time Diagram.
8/19/02
D
T2
T8
1
3
7
8
11
Features Section - added lead-free bullet.
Pin Characteristics Table - Changed CIN from 4pF max to 4pF typical.
Parameter Measurement Information - added Bank Skew diagram.
Application Information - added Recommenations for Unused Input and
Output Pins.
Ordering Information Table - added lead-free part number, marking and note.
Updated format throughout the data sheet.
2/27/06
ET8 11
13
Updated datasheet’s header/footer with IDT from ICS.
Removed ICS prefi x from Part/Order Number column.
Added Contact Page.
7/31/10
FT8
11 Ordering Information - removed leaded devices. PDN CQ-13-02.
Updated format throughout the data sheet.
1/22/15
