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72V51443L7-5BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
28
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
Figure 6. Serial Port Connection for Serial Programming
DFM
MRS
SENI SENO
MQ1
SI SO
SCLK
DFM
MRS
SENI SENO
MQ2
SI
SO
SCLK
DFM
MRS
SENI
SENO
MQn
SI
SO
SCLK
Serial Enable
Serial Input
Serial Clock
Default Mode
DFM = 0
Master Reset
Serial Loading
Complete
5939 drw10
Figure 5. Partial Reset
NOTES:
1. For a Partial Reset to be performed on a Queue, that Queue must be selected on both the write and read ports.
2. The queue must be selected a minimum of 2 clock cycles before the Partial Reset takes place, on both the write and read ports.
3. The Partial Reset must be LOW for a minimum of 1 WCLK and 1 RCLK cycle.
4. Writing or Reading to the queue (or a queue change) cannot occur until a minimum of 3 clock cycles after the Partial Reset has gone HIGH, on both the write and read ports.
5. The PAF flag output for Qx on the PAFn flag bus may update one cycle later than the active PAF flag.
6. The PAE flag output for Qx on the PAEn flag bus may update one cycle later than the active PAE flag.
WCLK
RCLK
RDADD
tAH
tAS
tQH
tQS
Qx
RADEN
r-2 r-1 r
PRS
r+2
r+1
t
PRSH
tPRSS
REN
tENS
r+3
tENS
tROV
OV
tRAE
PAE
5939 drw09
WEN
WADEN
tAH
tAS
WRADD
Qx
w-2 w-1 w w+1 w+2
t
QH
tQS
tENS
w+3
tENS
FF
tWFF
PAF
tWAF
Active Bus
PAF-Qx
(5)
tPAF
Active Bus
PAE-Qx
(6)
tPAE
tPRSH
tPRSS
29
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 7. Serial Programming
RCLK
WEN
SENO
(MQ1)
FF
WADEN/
FSTR
RADEN/
ESTR
OV
WCLK
5939 drw11
t
WFF
t
ENS
t
ROV
t
PCWQ
t
QS
t
QH
t
QS
t
QH
t
PCRQ
HIGH - Z
HIGH - Z
(Slave Device)
(Slave Device)
SO
(MQ1)
MRS
SCLK
SENI
(MQ1)
SI
(MQ1)
t
RSR
t
SENO
1st
2nd
nth
1st
2nd
nth
1st
2nd
nth
t
SENS
SENO
(MQ2)
SENO
(MQ8)
B
12
B
11
t
SDS
B
1n
t
SDH
B
21
B
22
B
2n
B
81
B
82
B
8n
B
21
B
22
B
2n
B
81
B
82
B
8n
t
SENO
t
SENO
t
SCLK
t
SCKL
t
SCKH
Programming Complete
1st Device in Chain 2nd Device in Chain Final Device in Chain
t
SDO
t
SDOP
t
SENOP
t
SENOP
NOTES:
1. SENI can be toggled during serial loading. Once serial programming of a device is complete, the SENI and SI inputs become transparent. SENI → SENO and SI → SO.
2. DFM is LOW during Master Reset to provide Serial programming mode, DF is don't care.
3. When SENO of the final device is LOW no further serial loads will be accepted.
4. n = 19+(Qx72); where Q is the number of queues required for the IDT72V51433/72V51443/72V51453.
5. This diagram illustrates 8 devices in expansion.
6. Programming of all devices must be complete (SENO of the final device is LOW), before any write or read port operations can take place, this includes queue selections.
30
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
DFM
MRS
SENI SENO
MQ1
WCLK
Serial Enable
(can be tied LOW)
WCLK
Default Mode
DFM = 1
Master Reset
Serial Loading
Complete
DFM
MRS
SENI SENO
MQ2
WCLK
DFM
MRS
SENI SENO
MQn
WCLK
RCLK
WEN
FF
WADEN/
FSTR
RADEN/
ESTR
OV
5939 drw11a
tWFF
tENS
tROV
tPCWQ
tQS
tQH
tQS
tQH
tPCRQ
HIGH - Z
HIGH - Z
(Slave Device)
(Slave Device)
SENO
(MQ1)
tSENO
SENO
(MQ2)
SENO
(MQ8)
tSENO
WCLK
MRS
1st Device in Chain
1st
2nd
nth
3rd
2nd Device in Chain
1st
2nd
nth
Final Device in Chain
1st
2nd
nth
Programming
Complete
tSENO
Serial Port Connection for Default Programming
SI SO XSI SOXSI SOX
Figure 8. Default Programming
NOTES:
1. This diagram illustrates multiple devices connected in expansion.
The SENO of the final device in a chain is the "programming complete" signal.
2. SENI of the first device in the chain can be held LOW
3. The SENO of a device should connect to the SENI of the next device in the chain.
The final device SENO is used to indicate programming complete.
4. When Default Programming is complete the SENO of the final device will go LOW.
5. SCLK is not used and can be tied LOW.
6. Programming of all devices must be complete (SENO of the final device is LOW),
before any write or read port operations can take place, this includes queue selections.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

72V51443L7-5BB

Mfr. #:
Buy 72V51443L7-5BB
Manufacturer:
IDT
Description:
FIFO X18 16Q 1M MULTI-QUE
Lifecycle:
New from this manufacturer.
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