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72V51443L7-5BB

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
37
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
RCLK
RADEN
Qout
REN
t
AH
t
AS
0001xxxx
RDADD
t
A
NULL QUEUE
SELECT
*A*
*B* *C* *E* *F*
t
QH
t
ENS
Q1 Wn-3 Q1 Wn-2 Q1 Wn-1
t
A
t
A
Q1 Wn
t
A
Q4 W0
FWFT
OV
t
ROV
t
ROV
5938 drw18
SELECT
NEW QUEUE
*D*
00000100
t
AH
t
AS
t
QH
t
QS
t
ENH
t
QS
Figure 16. Read Operation and Null Queue Select
NOTES:
1. The purpose of the Null queue operation is so that the user can stop reading a block (packet) of data from a queue without filling the 2 stage output pipeline with the next words
from that queue.
2. Please see Figure 17, Null Queue Flow Diagram.
Cycle:
*A* Null Q of device 0 (32nd queue) is selected, when word Wn-1 from previously selected Q1 is read.
*B* REN is HIGH and Wn (Last Word of the Packet) of Q1 is pipelined onto the O/P register.
Note: *B* and *C* are a minimum 2 RCLK cycles between Q selects.
*C* The Null Q is seen as an empty queue on the read side, therefore Wn of Q1 remains in the O/P register and OV goes HIGH.
*D* A new Q, Q4 is selected and the 1st word of Q4 will fall through present on the O/P register on cycle *F*.
5939 drw19
Queue 1
Memory
*A*
Null
Queue
*B*
Null
Queue
*C*
O/P Reg.
*D* *E* *F*
Null
Queue
Queue 4
Memory
Q1
Wn
Queue 4
Memory
O/P Reg. O/P Reg. O/P Reg. O/P Reg. O/P Reg.
Qn
Wn-1
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q1
Wn
Q4
W0
Q1
Wn
Q4
W1
Q4
W0
Figure 17. Null Queue Flow Diagram
38
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
WCLK
WADEN
tQHtQS
tAHtAS
WRADD
D
1
Q
5
PAF
(Device 1)
tAFLZ
5939 drw20
WEN
tENS
tAHtAS
tQH
tQS
tDH
tDS
W
D-m
Din
tWAF
tWAF
HIGH-Z
tENH
D
1
Q
9
PAF
(Device 2)
tFFHZ
12
D
1
Q
5
*B* *C* *E* *F*
*D*
*A*
Figure 18. Almost Full Flag Timing and Queue Switch
Figure 19. Almost Full Flag Timing
WCLK
WEN
PAF
RCLK
t
WAF
REN
5939 drw21
D - (m+1) words in Queue D - m words in Queue
1
2
1
D-(m+1) words
in Queue
t
WAF
t
ENH
t
ENS
t
SKEW2
t
ENH
t
ENS
t
CLKL
t
CLKL
Cycle:
*A* Queue 5 of Device 1 is selected on the write port. A queue within Device 2 had previously been selected. The PAF output of device 1 is High-Impedance.
*B* No write occurs.
*C* Word, Wd-m is written into Q5 causing the PAF flag to go from HIGH to LOW. The flag latency is 2 WCLK cycles + t
WAF.
*D* Queue 9 if device 1 is now selected for write operations. This queue is not almost full, therefore the PAF flag will update after a 2 WCLK + t
WAF latency.
*E* The PAF flag goes LOW based on the write 2 cycles earlier.
*F* The PAF flag goes HIGH due to the queue switch to Q9.
NOTE:
1. The waveform here shows the PAF flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost full boundary.
Flag Latencies:
Assertion: 2*WCLK + t
WAF
De-assertion: tSKEW2 + WCLK + tWAF
If tSKEW2 is violated there will be one extra WCLK cycle.
39
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 20. Almost Empty Flag Timing and Queue Switch
Figure 21. Almost Empty Flag Timing
RCLK
RADEN
t
QH
t
QS
t
AH
t
AS
RDADD
D1 Q12
PAE
(Device 1)
t
AELZ
5939 drw22
REN
t
AH
t
AS
t
QH
t
QS
t
OLZ
Qout
t
RAE
t
RAE
HIGH-Z
D1 Q15
PAE
(Device 2)
t
AEHZ
HIGH
HIGH-Z
t
A
D1 Q12 Wn
HIGH-Z
*B* *C* *E* *F**D**A*
t
A
D1 Q12 Wn+1
t
A
D1 Q15 W0
t
A
D1 Q15 W1
*G*
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n+1 words in Queue
t
RAE
t
SKEW2
t
RAE
12
REN
5939 drw23
t
ENS
t
ENH
n+2 words in Queue
n+1 words in Queue
Cycle:
*A* Queue 12 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q12 due to the FWFT operation. This read operation from Q12 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q15 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q12 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q15 due to the FWFT operation. The PAE flag goes HIGH to show that Q15 is not almost empty.
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + t
RAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

72V51443L7-5BB

Mfr. #:
Buy 72V51443L7-5BB
Manufacturer:
IDT
Description:
FIFO X18 16Q 1M MULTI-QUE
Lifecycle:
New from this manufacturer.
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