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72V51453L7-5BBI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
16
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
FUNCTIONAL DESCRIPTION
MASTER RESET
A Master Reset is performed by toggling the MRS input from HIGH to LOW
to HIGH. During a master reset all internal multi-queue device setup and control
registers are initialized and require programming either serially by the user via
the serial port, or using the default settings. During a master reset the state of
the following inputs determine the functionality of the part, these pins should be
held HIGH or LOW.
FM – Flag bus Mode
IW, OW – Bus Matching options
MAST – Master Device
ID0, 1, 2 – Device ID
DFM – Programming mode, serial or default
DF – Offset value for PAE and PAF
Once a master reset has taken place, the device must be programmed either
serially or via the default method before any read/write operations can begin.
See Figure 4, Master Reset for relevant timing.
PARTIAL RESET
A Partial Reset is a means by which the user can reset both the read and write
pointers of a single queue that has been setup within a multi-queue device.
Before a partial reset can take place on a queue, the respective queue must be
selected on both the read port and write port a minimum of 2 RCLK and 2 WCLK
cycles before the PRS goes LOW. The partial reset is then performed by toggling
the PRS input from HIGH to LOW to HIGH, maintaining the LOW state for at least
one WCLK and one RCLK cycle. Once a partial reset has taken place a minimum
of 3 WCLK and 3 RCLK cycles must occur before enabled writes or reads can
occur.
A Partial Reset only resets the read and write pointers of a given queue, a
partial reset will not effect the overall configuration and setup of the multi-queue
device and its queues.
See Figure 5, Partial Reset for relevant timing.
SERIAL PROGRAMMING
The multi-queue flow-control device is a fully programmable device, provid-
ing the user with flexibility in how queues are configured in terms of the number
of queues, depth of each queue and position of the PAF/PAE flags within
respective queues. All user programming is done via the serial port after a master
reset has taken place. Internally the multi-queue device has setup registers
which must be serially loaded, these registers contain values for every queue
within the device, such as the depth and PAE/PAF offset values. The
IDT72V51433/72V51443/72V51453 devices are capable of up to 16 queues
and therefore contain 16 sets of registers for the setup of each queue.
During a Master Reset if the DFM (Default Mode) input is LOW, then the device
will require serial programming by the user. It is recommended that the user
utilize a ‘C’ program provided by IDT, this program will prompt the user for all
information regarding the multi-queue setup. The program will then generate
a serial bit stream which should be serially loaded into the device via the serial
port. For the IDT72V51433/72V51443/72V51453 devices the serial program-
ming requires a total number of serially loaded bits per device, (SCLK cycles
with SENI enabled), calculated by: 19+(Qx72) where Q is the number of queues
the user wishes to setup within the device. Please refer to the separate
Application Note, AN-303 for recommended control of the serial programming
port.
Once the master reset is complete and MRS is HIGH, the device can be
serially loaded. Data present on the SI (serial in), input is loaded into the serial
port on a rising edge of SCLK (serial clock), provided that SENI (serial in
enable), is LOW. Once serial programming of the device has been successfully
completed the device will indicate this via the SENO (serial output enable) going
active, LOW. Upon detection of completion of programming, the user should
cease all programming and take SENI inactive, HIGH. Note, SENO follows SENI
once programming of a device is complete. Therefore, SENO will go LOW after
programming provided SENI is LOW, once SENI is taken HIGH again, SENO
will also go HIGH. The operation of the SO output is similar, when programming
of a given device is complete, the SO output will follow the SI input.
If devices are being used in expansion mode the serial ports of devices should
be cascaded. The user can load all devices via the serial input port control pins,
SI & SENI, of the first device in the chain. Again, the user may utilize the ‘C’
program to generate the serial bit stream, the program prompting the user for
the number of devices to be programmed. The SENO and SO (serial out) of
the first device should be connected to the SENI and SI inputs of the second
device respectively and so on, with the SENO & SO outputs connecting to the
SENI & SI inputs of all devices through the chain. All devices in the chain should
be connected to a common SCLK. The serial output port of the final device should
be monitored by the user. When SENO of the final device goes LOW, this
indicates that serial programming of all devices has been successfully com-
pleted. Upon detection of completion of programming, the user should cease all
programming and take SENI of the first device in the chain inactive, HIGH.
As mentioned, the first device in the chain has its serial input port controlled
by the user, this is the first device to have its internal registers serially loaded
by the serial bit stream. When programming of this device is complete it will take
its SENO output LOW and bypass the serial data loaded on the SI input to its
SO output. The serial input of the second device in the chain is now loaded with
the data from the SO of the first device, while the second device has its SENI
input LOW. This process continues through the chain until all devices are
programmed and the SENO of the final device goes LOW.
Once all serial programming has been successfully completed, normal
operations, (queue selections on the read and write ports) may begin. When
connected in expansion mode, the IDT72V51433/72V51443/72V51453 de-
vices require a total number of serially loaded bits per device to complete serial
programming, (SCLK cycles with SENI enabled), calculated by: n[19+(Qx72)]
where Q is the number of queues the user wishes to setup within the device,
where n is the number of devices in the chain.
See Figure 6, Serial Port Connection and Figure 7, Serial Programming for
connection and timing information.
DEFAULT PROGRAMMING
During a Master Reset if the DFM (Default Mode) input is HIGH the multi-
queue device will be configured for default programming, (serial programming
is not permitted). Default programming provides the user with a simpler,
however limited means by which to setup the multi-queue flow-control device,
rather than using the serial programming method. The default mode will
configure a multi-queue device such that the maximum number of queues
possible are setup, with all of the parts available memory blocks being allocated
equally between the queues. The values of the PAE/PAF offsets is determined
by the state of the DF (default) pin during a master reset.
For the IDT72V51433/72V51443/72V51453 devices the default mode will
setup 16 queues, each queue configured as follows: For the IDT72V51433 with
x9 input and x9 output ports, depth is 4,096, if one or both ports is x18, then the
depth is 2,048. For the IDT72V51443 with x9 input and x9 output ports, depth
is 8,192, if one or both ports is x18, then the depth is 4,096. For the IDT72V51453
with x9 input and x9 output ports, depth is 16,384, if one or both ports is x18,
then the depth is 8,192. For both devices the value of the PAE/PAF offsets is
determined at master reset by the state of the DF input. If DF is LOW then both
the PAE & PAF offset will be 8, if HIGH then the value is 128.
17
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
When configuring the IDT72V51433/72V51443/72V51453 devices in de-
fault mode the user simply has to apply WCLK cycles after a master reset, until
SENO goes LOW, this signals that default programming is complete. These clock
cycles are required for the device to load its internal setup registers. When a
single multi-queue device is used, the completion of device programming is
signaled by the SENO output of a device going from HIGH to LOW. Note, that
SENI must be held LOW when a device is setup for default programming mode.
When multi-queue devices are connected in expansion mode, the SENI of
the first device in a chain can be held LOW. The SENO of a device should connect
to the SENI of the next device in the chain. The SENO of the final device is used
to indicate that default programming of all devices is complete. When the final
SENO goes LOW normal operations may begin. Again, all devices will be
programmed with their maximum number of queues and the memory divided
equally between them. Please refer to Figure 8, Default Programming.
WRITE QUEUE SELECTION & WRITE OPERATION
The IDT72V51433/72V51443/72V51453 multi-queue flow-control devices
have up to 16 queues that data can be written into via a common write port using
the data inputs, Din, write clock, WCLK and write enable, WEN. The queue
address present on the write address bus, WRADD during a rising edge on
WCLK while write address enable, WADEN is HIGH, is the queue selected for
write operations. The state of WEN is don’t care during the write queue selection
cycle. The queue selection only has to be made on a single WCLK cycle, this
will remain the selected queue until another queue is selected, the selected
queue is always the last queue selected.
The write port is designed such that 100% bus utilization can be obtained.
This means that data can be written into the device on every WCLK rising edge
including the cycle that a new queue is being addressed. When a new queue
is selected for write operations the address for that queue must be present on
the WRADD bus during a rising edge of WCLK provided that WADEN is HIGH.
A queue to be written to need only be selected on a single rising edge of WCLK.
All subsequent writes will be written to that queue until a new queue is selected.
A minimum of 2 WCLK cycles must occur between queue selections on the write
port. On the next WCLK rising edge the write port discrete full flag will update
to show the full status of the newly selected queue. On the second rising edge
of WCLK, data present on the data input bus, Din can be written into the newly
selected queue provided that WEN is LOW and the new queue is not full. The
cycle of the queue selection and the next cycle will continue to write data present
on the data input bus, Din into the previous queue provided that WEN is active
LOW.
If WEN is HIGH, inactive for these 2 clock cycles, then data will not be written
in to the previous queue.
If the newly selected queue is full at the point of its selection, then writes to that
queue will be prevented, a full queue cannot be written into.
In the 16 queue multi-queue device the WRADD address bus is 7 bits wide.
The least significant 4 bits are used to address one of the 16 available queues
within a single multi-queue device. The most significant 3 bits are used when
a device is connected in expansion mode, up to 8 devices can be connected
in expansion, each device having its own 3 bit address. The selected device
is the one for which the address matches a 3 bit ID code, which is statically setup
on the ID pins, ID0, ID1, and ID2 of each individual device.
Note, the WRADD bus is also used in conjunction with FSTR (almost full flag
bus strobe), to address the almost full flag bus sector during direct mode of
operation.
Refer to Table 1, for Write Address bus arrangement. Also, refer to Figure
9, Write Queue Select, Write Operation and Full flag Operation and Figure
11, Full Flag Timing Expansion Mode for timing diagrams.
TABLE 1 — WRITE ADDRESS BUS, WRADD[6:0]
Operation WCLK WADEN FSTR
WRADD[6:0]
Write Queue
Select
10
01
Device Select
(Compared to
ID0,1,2)
Write Queue Address
(4 bits = 16 Queues)
654 32 10
765432 0
Device Select
(Compared to
ID0,1,2)
X X X Sector
Address
PAFn Sector
Select
Q0 : Q7 → PAF0 : PAF7
Sector
Address
Queue Status on PAFn Bus
0
1
Q8 : Q15 → PAF0 : PAF7
5939 drw05
1
X
18
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
READ QUEUE SELECTION & READ OPERATION
The multi-queue flow-control device has up to 16 queues that data is read
from via a common read port using the data outputs, Qout, read clock, RCLK
and read enable, REN. An output enable, OE control pin is also provided to allow
High-Impedance selection of the Qout data outputs. The multi-queue device
read port operates in a mode similar to “First Word Fall Through” on a traditional
IDT FIFO, but with the added feature of data output pipelining. This data
pipelining on the output port allows the user to achieve 100% bus utilization,
which is the ability to read out a data word on every rising edge of RCLK
regardless of whether a new queue is being selected for read operations.
The queue address present on the read address bus, RDADD during a rising
edge on RCLK while read address enable, RADEN is HIGH, is the queue
selected for read operations. A queue to be read from need only be selected
on a single rising edge of RCLK. All subsequent reads will be read from that
queue until a new queue is selected. A minimum of 2 RCLK cycles must occur
between queue selections on the read port. Data from the newly selected queue
will be present on the Qout outputs after 2 RCLK cycles plus an access time,
provided that OE is active, LOW. On the same RCLK rising edge that the new
queue is selected, data can still be read from the previously selected queue,
provided that REN is LOW, active and the previous queue is not empty on the
following rising edge of RCLK a word will be read from the previously selected
queue regardless of REN due to the fall through operation, (provided the queue
is not empty). Remember that OE allows the user to place the Qout, data output
bus into High-Impedance and the data can be read onto the output register
regardless of OE.
When a queue is selected on the read port, the next word available in that
queue (provided that the queue is not empty), will fall through to the output
register after 2 RCLK cycles. As mentioned, in the previous 2 RCLK cycles to
the new data being available, data can still be read from the previous queue,
provided that the queue is not empty. At the point of queue selection, the 2-stage
internal data pipeline is loaded with the last word from the previous queue and
the next word from the new queue, both these words will fall through to the output
register consecutively upon selection of the new queue. This pipelining effect
provides the user with 100% bus utilization, but brings about the possibility that
a “NULL” queue may be required within a multi-queue device. Null queue
operation is discussed in the next section on.
If an empty queue is selected for read operations on the rising edge of RCLK,
on the same RCLK edge and the following RCLK edge, 2 final reads will be made
from the previous queue, provided that REN is active, LOW. On the next RCLK
rising edge a read from the new queue will not occur, because the queue is
empty. The last word in the data output register (from the previous queue), will
remain there, but the output valid flag, OV will go HIGH, to indicate that the data
present is no longer valid.
The RDADD bus is also used in conjunction with ESTR (almost empty flag
bus strobe), to address the almost empty flag bus of a respective device during
direct mode of operation. In the 16 queue multi-queue device the RDADD
address bus is 8 bits wide. The least significant 4 bits are used to address one
of the 16 available queues within a single multi-queue device. The 5th least
significant bit is used to select a "Null" Queue. During a Null-Q selection the 4
LSB's are don't care. The Null-Q is seen as an empty queue on the read port.
Null-Q operation is discussed in more detail in a separate section. The most
significant 3 bits are used when a device is connected in expansion mode, up
to 8 devices can be connected in expansion, each device having its own 3 bit
address. The selected device is the one for which the address matches a 3 bit
ID code, which is statically setup on the ID pins, ID0, ID1, and ID2 of each
individual device.
Refer to Table 2, for Read Address bus arrangement. Also, refer to Figures
12,14 & 15 for read queue selection and read port operation timing diagrams.
Operation RCLK RADEN ESTR
RDADD[7:0]
Read Queue
Select
10
01
Device Select
(Compared to
ID0,1,2)
Read Queue Address
(4 bits = 16 Queues)
7 6 5 4 3210
4321 0
Device Select
(Compared to
ID0,1,2)
X X X Sector
Address
PAEn Sector
Select
Q0 : Q7 → PAE0 : PAE7
Sector
Address
Queue Status on PAEn Bus
0
1
Q8 : Q15 → PAE0 : PAE7
5939 drw06
X
Null-Q
Select
Pin
TABLE 2 — READ ADDRESS BUS, RDADD[7:0]
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

72V51453L7-5BBI

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