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72V51453L7-5BBI

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50
31
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 9. Write Queue Select, Write Operation and Full Flag Operation
WCLK
WADEN
tQH
tQS
tAH
tAS
WRADD
Q
x
FF
tWFF
5939 drw12
WEN
tENS
tAH
tAS
Q
y
tQH
tQS
tDH
tDS
Q
X
W
D
tDH
Q
y
W
D-2
W
D-1
Q
y
tDH
Din
tWFF
tWFF
Previous Q Status
No Writes
Queue Full
*A* *B* *C* *D* *E* *F* *G*
tDS
Q
y
W
D
tDS
tDH
tENH
tWFF
tWFF
RCLK
tSKEW1
tQS tQH
REN
tENS
RDADD
Q
y
RADEN
Qout
tA
Previous Q, Word, W Previous Q, W
+1
PFT
tA
Qy, W
0
PFT
tA tA
Qy, W
1
Qy, W
2
*H* *I* *J*
tAS
tAH
*AA* *BB* *CC* *DD* *EE* *FF*
tDS
NOTE:
OE is active LOW.
Cycle:
*A* Queue, Qx is selected on the write port.
The FF flag is providing status of a previously selected queue, within the same device.
*AA* Queue, Qy is selected for read operations.
*B* The FF flag output updates to show the status of Qx, it is not full.
*BB* Word W+1 is read from the previous queue regardless of REN due to FWFT.
*C* Word, Wd is written into Qx. This causes Qx to go full.
*CC* Word, W0 is read from Qy regardless of REN, this is due to the FWFT effect.
*D* Queue, Qy is selected within the same device as Qx. A write to Qx cannot occur on this cycle because it is full, FF is LOW.
*DD* No reads occur, REN is HIGH.
*E* Again, a write to Qx cannot occur on this cycle because it is full, FF is LOW. The FF flag updates after time t
WFF to show that queue, Qy is not full.
*EE* Word, W1 is read from Qy, this causes Qy to go “not full”, FF flag goes HIGH after time, t
SKEW1 + tWFF. Note, if tSKEW1 is violated the time FF HIGH will be: tSKEW1 + WCLK + tWFF.
*F* Word, Wd-2 is written into Qy.
*FF* Word, W2 is read from Qy.
*G* Word, Wd-1 is written into Qy.
*H* Word, Wd is written into Qy, this causes Qy to go full, FF goes LOW.
*I* No writes occur to Qy.
*J* Qy goes “not full” based on reading word W1 from Qy on cycle *EE*.
32
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
5939 drw12a
W1 W2 W3
WCLK
t
ENH
WEN
Dn
t
DH
t
DS
t
DS
t
DH
t
DS
t
DH
RCLK
t
SKEW1
12
t
ENS
REN
t
A
W1 Qy
FWFT
t
A
t
A
W2 Qy
FWFT
W3 QyLast Word Read Out of Queue
Qout
t
ROV
OV
t
ROV
t
ENS
Figure 10. Write Operations & First Word Fall Through
NOTES:
1. Qy has previously been selected on both the write and read ports.
2. OE is LOW.
3. The First Word Latency = t
SKEW1 + RCLK + tA. If tSKEW1 is violated an additional RCLK cycle must be added.
33
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
WCLK
WADEN
t
QH
t
QS
t
AH
t
AS
WRADD
D
1
Q
12
FF
(Device 1)
t
FFLZ
5939 drw13
WEN
t
ENS
t
AH
t
AS
t
AH
t
AS
t
QH
t
QS
D
2
Q
9
t
QH
t
QS
t
DH
t
DS
W
D
D
1 Q12
t
DH
t
DS
Din
t
WFF
t
WFF
HIGH-Z
RCLK
1
2
t
ENH
t
ENS
t
ENH
Addr=001
1100
D
1
Q
5
t
WFF
W
D
D
1 Q5
t
FFHZ
t
WFF
HIGH-Z
FF
(Device 2)
t
FFHZ
HIGH-Z
t
FFLZ
t
SKEW1
Addr=001
0101
t
AH
t
AS
RDADD
D
1
Q
5
t
QH
t
QS
RADEN
*A* *B* *C* *D* *E* *F* *G* *H* *I*
No Write
*J*
Qout
t
A
t
A
Previous Q W
X-1
Previous Q W
X
PFT
D
1
-Q
5
Word W
0
PFT
*AA* *BB* *CC*
Figure 11. Full Flag Timing in Expansion Mode
NOTE:
1. REN = HIGH.
Cycle:
*A* Queue, Q12 of device 1 is selected on the write port.
The FF flag of device 1 is in High-Impedance, the write port of device 2 was previously selected.
WEN is HIGH so no write occurs.
*AA* Queue, Q5 of device 1 is selected on the read port.
*B* The FF flag of device 2 goes to High-Impedance and the FF flag of device 1 goes to Low-Impedance, logic HIGH indicating that D1 Q12 is not full.
WEN is HIGH so no write occurs.
*BB* Word, Wx is read from the previously selected queue, (due to FWFT).
*C* Word, Wd is written into Q12 of D1. This write operation causes Q12 to go full, FF goes LOW.
*CC* The first word from Q5 of D1 selected on cycle *AA* is read out, this occurred regardless of REN due to FWFT. This read caused Q5 to go not full, therefore the FF flag will go HIGH after: t
SKEW1 + tWFF.
Note if t
SKEW1 is violated the time to FF flag HIGH is tSKEW1 + WLCK + tWFF.
*D* Queue, Q5 of device 1 is selected on the write port. No write occurs on this cycle.
*E* The FF flag updates to show the status of D1 Q5, it is not full, FF goes HIGH.
*F* Word, Wd is written into Q5 of D1. This causes the queue to go full, FF goes LOW.
*G* No write occurs regardless of WEN, the FF flag is LOW preventing writes.
*H* The FF flag goes HIGH due to the read from Q5 of D1 on cycle *CC*. (This read is not an enabled read, it is due to the FWFT operation).
*I* Queue, Q9 of device 2 is selected on the write port.
*J* The FF flag of device 1 goes to High-Impedance, this device was deselected on the write port on cycle *I*. The FF flag of device 2 goes to Low-Impedance and provides status of Q9 of D2.
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P42P43-P45P46-P48P49-P50

72V51453L7-5BBI

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Description:
IC MULTI-QUEUE FLOW-CTRL 256BGA
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New from this manufacturer.
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