39
IDT72V51433/72V51443/72V51453 3.3V, MULTI-QUEUE FLOW-CONTROL DEVICES
(16 QUEUES) 18 BIT WIDE CONFIGURATION 589,824, 1,179,648 and 2,359,296 bits
COMMERCIAL AND INDUSTRIAL
TEMPERATURE RANGES
Figure 20. Almost Empty Flag Timing and Queue Switch
Figure 21. Almost Empty Flag Timing
RCLK
RADEN
t
QH
t
QS
t
AH
t
AS
RDADD
D1 Q12
PAE
(Device 1)
t
AELZ
5939 drw22
REN
t
AH
t
AS
t
QH
t
QS
t
OLZ
Qout
t
RAE
t
RAE
HIGH-Z
D1 Q15
PAE
(Device 2)
t
AEHZ
HIGH
HIGH-Z
t
A
D1 Q12 Wn
HIGH-Z
*B* *C* *E* *F**D**A*
t
A
D1 Q12 Wn+1
t
A
D1 Q15 W0
t
A
D1 Q15 W1
*G*
WCLK
t
ENH
t
CLKH
t
CLKL
WEN
PAE
RCLK
t
ENS
n+1 words in Queue
t
RAE
t
SKEW2
t
RAE
12
REN
5939 drw23
t
ENS
t
ENH
n+2 words in Queue
n+1 words in Queue
Cycle:
*A* Queue 12 of Device 1 is selected on the read port. A queue within Device 2 had previously been selected. The PAE flag output and the data outputs of device 1 are High-Impedance.
*B* No read occurs.
*C* The PAE flag output now switches to device 1. Word, Wn is read from Q12 due to the FWFT operation. This read operation from Q12 is at the almost empty boundary, therefore
PAE will go LOW 2 RCLK cycles later.
*D* Q15 of device 1 is selected.
*E* The PAE flag goes LOW due to the read from Q12 2 RCLK cycles earlier. Word Wn+1 is read out due to the FWFT operation.
*F* Word, W0 is read from Q15 due to the FWFT operation. The PAE flag goes HIGH to show that Q15 is not almost empty.
NOTE:
1. The waveform here shows the PAE flag operation when no queue switches are occurring and a queue selected on both the write and read ports is being written to then read
from at the almost empty boundary.
Flag Latencies:
Assertion: 2*RCLK + t
RAE
De-assertion: tSKEW2 + RCLK + tRAE
If tSKEW2 is violated there will be one extra RCLK cycle.