13
FN6582.1
November 3, 2009
FIGURE 21. TOTAL HARMONIC DISTORTION vs FREQUENCY
Die Characteristics
SUBSTRATE POTENTIAL (POWERED UP):
GND (DFN Paddle Connection: Tie to GND or Float)
TRANSISTOR COUNT:
432
PROCESS:
Submicron CMOS
Typical Performance Curves T
A
= +25°C, Unless Otherwise Specified (Continued)
FREQUENCY (Hz)
20 100 200 1k 2k 10k 20k
V
BIAS
= 0VDC
R
L
=32Ω
V+ = 3.3V
707mV
RMS
177mV
RMS
0.01
0.02
0.03
0.04
0.05
THD+N (%)
0
360mV
RMS
ISL54063, ISL54064
14
FN6582.1
November 3, 2009
ISL54063, ISL54064
Thin Dual Flat No-Lead Plastic Package (TDFN)
//
NX (b)
SECTION "C-C"
FOR ODD TERMINAL/SIDE
e
CC
5
C
L
TERMINAL TIP
(A1)
BOTTOM VIEW
A
6
AREA
INDEX
C
C
0.10
0.08
SIDE VIEW
0.10
2X
E
A
B
C0.10
D
TOP VIEW
CB
2X
6
8
AREA
INDEX
NX L
E2
E2/2
REF.
e
N
(Nd-1)Xe
(DATUM A)
(DATUM B)
5
0.10
87
D2
BAC
N-1
12
PLANE
SEATING
C
A
A3
NX b
D2/2
NX k
L1
9
L
M
L10.3x3A
10 LEAD THIN DUAL FLAT NO-LEAD PLASTIC PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A
0.70 0.75 0.80
-
A1
- - 0.05
-
A3
0.20 REF
-
b
0.20 0.25 0.30
5, 8
D
2.95 3.0 3.05
-
D2
2.25 2.30 2.35
7, 8
E
2.95 3.0 3.05
-
E2
1.45 1.50 1.55
7, 8
e
0.50 BSC
-
k
0.25 - -
-
L
0.25 0.30 0.35
8
N
10
2
Nd
5
3
Rev. 3 3/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd refers to the number of terminals on D.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Dimensions D2 and E2 are for the exposed pads which provide
improved electrical and thermal performance.
8. Nominal dimensions are provided to assist with PCB Land
Pattern Design efforts, see Intersil Technical Brief TB389.
9. Compliant to JEDEC MO-229-WEED-3 except for D2
dimensions.
15
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems.
Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without
notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and
reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result
from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com
FN6582.1
November 3, 2009
ISL54063, ISL54064
Ultra Thin Quad Flat No-Lead Plastic Package (UTQFN)
6
B
E
A
D
0.10 C
2X
C
0.05 C
A
0.10 C
A1
SEATING PLANE
INDEX AREA
21
N
TOP VIEW
SIDE VIEW
NX (b)
SECTION "C-C"
e
CC
5
C
L
TERMINAL TIP
(A1)
L
0.10 C
2X
L1
e
NX L
BOTTOM VIEW
5
7
21
PIN #1 ID
(DATUM A)
(DATUM B)
0.10 M C A B
0.05 M C
NX b
10X
5
0.50
0.20
0.40
1.80
0.40
0.20
2.20
1.00
0.60
1.00
LAND PATTERN
10
L10.1.8x1.4A
10 LEAD ULTRA THIN QUAD FLAT NO-LEAD PLASTIC
PACKAGE
SYMBOL
MILLIMETERS
NOTESMIN NOMINAL MAX
A 0.45 0.50 0.55 -
A1 - - 0.05 -
A3 0.127 REF -
b 0.15 0.20 0.25 5
D 1.75 1.80 1.85 -
E 1.35 1.40 1.45 -
e 0.40 BSC -
L 0.35 0.40 0.45 -
L1 0.45 0.50 0.55 -
N102
Nd 2 3
Ne 3 3
θ
0-12
4
Rev. 3 6/06
NOTES:
1. Dimensioning and tolerancing conform to ASME Y14.5-1994.
2. N is the number of terminals.
3. Nd and Ne refer to the number of terminals on D and E side,
respectively.
4. All dimensions are in millimeters. Angles are in degrees.
5. Dimension b applies to the metallized terminal and is measured
between 0.15mm and 0.30mm from the terminal tip.
6. The configuration of the pin #1 identifier is optional, but must be
located within the zone indicated. The pin #1 identifier may be
either a mold or mark feature.
7. Maximum package warpage is 0.05mm.
8. Maximum allowable burrs is 0.076mm in all directions.
9. JEDEC Reference MO-255.
10. For additional information, to assist with the PCB Land Pattern
Design effort, see Intersil Technical Brief TB389.

ISL54063IRTZ-T

Mfr. #:
Manufacturer:
Renesas / Intersil
Description:
Analog Switch ICs SUB-OHM SWITCH DL SPDT W/NEG SWING10LD
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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