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874S02BMILF

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17
1©2016 Integrated Device Technology, Inc January 26, 2016
PLL_SEL
CLK
nCLK
FB_IN
nFB_IN
SEL0
SEL1
SEL2
SEL3
MR
PLL
8:1, 4:1, 2:1, 1:1,
1:2, 1:4, 1:8
Q
nQ
QF
B
nQFB
0
1
÷1, ÷2, ÷4, ÷8,
÷16, ÷32, ÷64
Pullup
Pullup
Pullup
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
Pulldown
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
QFB
nQFB
V
DDO
SEL2
FB_IN
nFB_IN
MR
nCLK
CLK
GND
SEL1
SEL0
V
DD
PLL_SEL
V
DDA
SEL3
GND
Q
nQ
V
DDO
General Description
The 874S02I is a highly versatile 1:1 Differential- to-LVDS Clock
Generator and a member of the family of High Performance Clock
Solutions from IDT. The 874S02I has a fully integrated PLL and
can be configured as a zero delay buffer, multiplier or divider, and
has an output frequency range of 62.5MHz to 1GHz. The
reference divider, feedback divider and output divider are each
programmable, thereby allowing for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8. The external
feedback allows the device to achieve “zero delay” between the
input clock and the output clocks. The PLL_SEL pin can be used
to bypass the PLL for system test and debug purposes. In bypass
mode, the reference clock is routed around the PLL and into the
internal output dividers.
Features
• One differential LVDS output pair and
one differential feedback output pair
• One differential clock input pair
• CLK/nCLK can accept the following differential input levels:
LVPECL, LVDS, LVHSTL, SSTL
• Input frequency range: 62.5MHz to 1GHz
• Output frequency range: 62.5MHz to 1GHz
• VCO range: 500MHz - 1GHz
• External feedback for "zero delay" clock regeneration with
configurable frequencies
• Programmable dividers allow for the following output-to-input
frequency ratios: 8:1, 4:1, 2:1, 1:1, 1:2, 1:4, 1:8
• Cycle-to-cycle jitter: 35ps (maximum)
• Static phase offset: ±100ps
• Full 3.3V supply mode
• -40°C to 85°C ambient operating temperature
• Available in lead-free packages
874S02I
20-Lead SOIC
7.5mm x 12.8mm x 2.3mm package body
M Package
Top View
Block Diagram
Pin Assignment
1:1 Differential-to-LVDS Zero Delay
Clock Generator
874S02I
Data Sheet
2©2016 Integrated Device Technology, Inc January 26, 2016
874S02I Data Sheet
Table 1. Pin Descriptions
NOTE: Pullup and Pulldown refer to internal input resistors. See Table 2, Pin Characteristics, for typical values.
Table 2. Pin Characteristics
Number Name Type Description
1 CLK Input Pulldown Non-inverting differential clock input.
2 nCLK Input Pullup Inverting differential clock input.
3 MR Input Pulldown
Active HIGH Master Reset. When logic HIGH, the internal dividers are reset
causing the true outputs Q and QFB to go low and the inverted outputs nQ and
nQFB to go high. When logic LOW, the internal dividers and the outputs are
enabled. LVCMOS / LVTTL interface levels.
4 nFB_IN Input Pullup
Inverting differential feedback input to phase detector for regenerating clocks
with “Zero Delay.” Connect to pin 8.
5 FB_IN Input Pulldown
Non-inverted differential feedback input to phase detector for regenerating
clocks with “Zero Delay.” Connect to pin 9.
6, 15,
19, 20
SEL2, SEL3,
SEL0, SEL1
Input Pulldown Determines output divider values in Table 3. LVCMOS / LVTTL interface levels.
7, 11 V
DDO
Power Output supply pins.
8, 9 nQFB, QFB Output Differential feedback output pair. HSTL interface levels.
10, 14 GND Power Power supply ground.
12, 13 nQ, Q Output Differential clock output pair. HSTL interface levels.
16 V
DDA
Power Analog supply pin.
17 PLL_SEL Input Pullup
PLL select. Selects between the PLL and reference clock as the input to the
dividers. When LOW, selects reference clock. When HIGH, selects PLL.
LVCMOS/LVTTL interface levels.
18 V
DD
Power Core supply pin.
Symbol Parameter Test Conditions Minimum Typical Maximum Units
C
IN
Input Capacitance 2 pF
R
PULLUP
Input Pullup Resistor 50 k
R
PULLDOWN
Input Pulldown Resistor 50 k
3©2016 Integrated Device Technology, Inc January 26, 2016
874S02I Data Sheet
Function Tables
Table 3A. Control Input Function Table
*NOTE: VCO frequency range for all configurations above is 500MHz to 1GHz.
Inputs Outputs
PLL_SEL = 1
PLL Enable Mode
SEL3 SEL2 SEL1 SEL0 Reference Frequency Range (MHz)* Q/nQ
0000 500 - 1000 ÷1
0001 250 - 500 ÷1
0010 125 - 250 ÷1
0011 62.5 - 125 ÷1
0100 500 - 1000 ÷2
0101 250 - 500 ÷2
0110 125 - 250 ÷2
0111 500 - 1000 ÷4
1000 250 - 500 ÷4
1001 500 - 1000 ÷8
1010 250 - 500 x2
1011 125 - 250 x2
1100 62.5 - 125 x2
1101 125 - 250 x4
1110 62.5 - 125 x4
1111 62.5 - 125 x8
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P17

874S02BMILF

Mfr. #:
Buy 874S02BMILF
Manufacturer:
IDT
Description:
Clock Generators & Support Products 1 LVDS OUT BUFFER
Lifecycle:
New from this manufacturer.
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