12©2016 Integrated Device Technology, Inc January 26, 2016
874S02I Data Sheet
All the resistors and capacitors are size 0603.
Power and Grounding
Place the decoupling capacitors as close as possible to the power
pins. If space allows, placement of the decoupling capacitor on
the component side is preferred. This can reduce unwanted
inductance between the decoupling capacitor and the power pin
caused by the via.
Maximize the power and ground pad sizes and number of vias
capacitors. This can reduce the inductance between the power
and ground planes and the component power and ground pins.
The RC filter consisting of R7, C11, and C16 should be placed as
close to the V
DDA
pin as possible.
Clock Traces and Termination
Poor signal integrity can degrade the system performance or
cause system failure. In synchronous high-speed digital systems,
the clock signal is less tolerant to poor signal integrity than other
signals. Any ringing on the rising or falling edge or excessive ring
back can cause system failure. The shape of the trace and the
trace delay might be restricted by the available space on the
board and the component location. While routing the traces, the
clock signal traces should be routed first and should be locked
prior to routing other signal traces.
• The 100 differential output traces should have the same
length.
• Avoid sharp angles on the clock trace. Sharp angle turns
cause the characteristic impedance to change on the
transmission lines.
• Keep the clock traces on the same layer. Whenever possible,
avoid placing vias on the clock traces. Placement of vias on
the traces can affect the trace characteristic impedance and
hence degrade signal integrity.
• To prevent cross talk, avoid routing other signal traces in
parallel with the clock traces. If running parallel traces is
unavoidable, allow a separation of at least three trace widths
between the differential clock trace and the other signal trace.
• Make sure no other signal traces are routed between the
clock trace pair.
• The series termination resistors should be located as close to
the driver pins as possible.
Figure 5B. PCB Board Layout for 874S02I
100 Ohm
Differential
Traces
VDDA
VDD
C2
U1
R7
C16
VDDO
GND
C4
C1
ICS8745B-21
VIA
C11
ICS874S02I
