NCP5392Q
http://onsemi.com
19
Oscillator and Triangle Wave Generator
A programmable precision oscillator is provided. The
oscillator’s frequency is programmed by the resistance
connec ted from the ROSC pin to ground. The user will
usually form this resistance from two resistors in orde r to
crea te a voltage divider that uses the ROSC output voltage
as the reference for creating the current limit setpoint
voltage. The oscillator frequency range is 100 kHz per
phase to 1.0 MHz per phase. The oscillator generates up to
4 symmetrical triangle waveforms with amplitude between
1.3 V and 2.3 V. The triangle waves have a phase delay
between them such that for 2--, 3-- and 4--phase operation
the PWM outputs are separated by 180, 120, and 90 angular
degrees, respectively.
PWM Comparators with Hysteresis
Four PWM comparators receive an error signal at their
noninverting input. Each comparator receives one of the
triangle waves at its inverting output. The output of each
comparator generates the PWM outputs G1, G2, G3, and G4.
During steady state operation, the duty cycle will center
on the valley of the triangle waveform, with steady state
duty cycle calculated by V
out
/V
in
. During a transient event,
both high and low comparator output transitions shift phase
to the points where the error signal inte rsects the down and
up ramp of the triangle wave .
PROTECTION FEATURES
Power Saving Mode
Upon receiving PSI low command, or VID down with
Auto--PSI enabled, the NCP5392Q enters power saving
mode with only single phase running. The device operates
in power saving mode to maintain a high power efficiency
and good transient performance.
Undervoltage Lockout
An undervolt age lockout (UVLO) senses the V
CC
input.
During power --up, the input vol tage to the control ler is
monitored, and the PWM outputs and the soft--start circuit
are disabled until the input voltage exceeds the threshold
voltage of t he UVLO compa rator. The UVLO comparator
incorporates hysteresis to avoid chattering.
12VMON UVLO a nd VIN Information
12V UVLO senses the 12V power supply by connecting
it t o the 12VMON pin through an appropriate resistor
divider. During power-up, t he 12VMON is monitored and
the PWM outputs and soft-start circuit are disabled until t he
voltage exceeds the threshold of its UVLO comparator.
The UVLO comparator incorporates hysteresis to avoid
chattering.
Overcurrent Shutdown
A programmable overc urrent function is incorporated
within the IC. A comparator and latch make up this
function. The inverting input of the comparator is
connected to the ILIM pin. The voltage at this pin sets the
maximum output current the convert er can produce. The
ROSC pin provides a convenient and accurate reference
voltage from which a resistor divider can create the
overcurre nt setpoint voltage. Although not actually
disabled, tying the ILIM pin directly to the ROSC pin sets
the limit above useful levels -- effectively disabling
overcurre nt shutdown. The comparator noninverting input
is the summed current information from the VDRP minus
offset voltage. The overcurrent latch is set when the current
information exceeds the voltage at the ILIM pin. The
outputs are pulled low, and the soft--start is pulled low. The
outputs will remain disabled until the V
CC
voltage is
removed and re--applied, or the ENABLE input is brought
low and the n high.
Output Overvoltage and Undervoltage Protection and
Power Good Monitor
An output voltage monitor is incorporated. During normal
operation, if the output voltage is 180 mV (typical) over the
DAC voltage, the VR_RDY goes low, the DRVO N signal
remains high, the PWM outputs are set low. The outputs will
remain disabled until the V
CC
voltage is removed and
reapplied. During normal operation, if the output voltage falls
more than 35 0 mV below th e DA C setting, the VR_R D Y p in
will be set low unt il the output voltage rises.
Soft--Start
The VR11 mode ra mps V
core
to 1.1 V boot voltage at a
fixed rate of 0.8 mV/mS, pauses at 1.1 V for around 500 mS,
reads the VID pins to determine the DAC setting. Then
ramps V
core
to the final DAC setting at the Dynamic VID
slew rate of up to 12.5 mV/mS. Typical VR11 soft--start
sequence s are shown in the following graphs (Figure 9 and
10).
