NCP5392Q
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28
SYSTEM TIMING DIAGRAM
Figure 24. Normal Startup
500 ms
500 ms
3.5 ms
VR_RDY
VSP--VSN
VID
DRVON
EN
UVLO
5 V (Controller)
1.5 ms
1 msmin
Valid VID
12 V (Gate Driver)
UVLO
Figure 25. Driver UVLO Limited Startup
500 ms
500 ms
3.5 ms
VR_RDY
VSP--VSN
VID
DRVON
EN
UVLO
5 V (Controller)
POR
1ms
1.5 ms
1 msmin
UVLO
Valid VID
12 V (Gate Driver)
NCP5392Q
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29
Figure 26. OVP Shutdown
185 mV
VSP = VID -- 19 mV
DRVON = High
VR_RDY
Diffout ~ 1.3 V
185 mV
12345678
12345678
Figure 27. Non--PSI Current Limit
VDRP
VR_RDY
DRVON
I
limit
+1.3
NCP5392Q
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30
PACKAGE DIMENSIONS
QFN40 6x6, 0.5P
CASE 488AR --01
ISSUE A
SEATING
40X
K
0.15 C
(A3)
A
A1
D2
b
1
11
20
21
40
2X
2X
E2
40X
10
30
40X
L
40X
BOTTOM VIEW
EXPOSED PAD
TOP VIEW
SIDE VIEW
D A B
E
0.15
C
PIN ONE
LOCATION
0.10 C
0.08 C
C
31
e
A0.10 B
C
0.05
C
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ASME Y14.5M, 1994.
2. CONTROLLING DIMENSIONS: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED
TERMINAL AND IS MEASURED BETWEEN
0.25 AND 0.30mm FROM TERMINAL
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
DIM MIN MAX
MILLIMETERS
A 0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b 0.18 0.30
D 6.00 B SC
D2 4.00 4.20
E 6.00 BSC
4.20E2 4.00
e 0.50 BSC
L 0.30 0.50
K 0 . 2 0 -- -- --
36X
PLANE
DIMENSIONS: MILLIMETERS
0.50 PITCH
4.20
0.30
4.20
40X
36X
0.65
40X
6.30
6.30
*For additional information on our Pb--Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
1
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NCP5392QMNR2G

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Description:
IC REG CTRLR VR11 4OUT 40QFN
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