NCP5392Q
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25
Actual DCR increases by temperature, the system can be
thermally compensated to cancel this effect to a great
degree by adding an NTC in parallel with R
NOR
to reduce
the droop gain as the temperature increases. The NTC
device is nonlinear. Putting a resistor in series with the NTC
helps make the device appear more linear with
temperature. The series resistor is split and inserted on both
sides of the NTC to reduce noise inj ection into the feedback
loop. The rec ommended tot al value for R
ISO1
plus R
ISO2
is
approximately 1.0 kΩ.
The output impedance varies with inductor temperature
by the e quation:
Z
out
(T) =
R
FB
DCR
25C
(1 + 0.00393 (T 25)) A
CSSUM
A
DRP
R
DRP
(eq. 15)
By incl uding the NTC R
T2
and the series isolation resistors the new equation becomes:
Z
out
(T) =
R
FB
DCR
25C
(1 + 0.00393 (T 25)) A
CSSUM
R
NOR
(R
ISO1
+R
ISO2
+R
T2
)
(R
NOR
+R
ISO1
+R
ISO2
+R
T2
)R
SUM
R
DRP
(eq. 16)
The typica l equation of an NTC is based on a curve fit
Equation 17
RT2(T) = RT2
25C
e
β
1
273+T
1
298
(eq. 17)
The demo board use a 10 kΩ NTC with a β value of 3740.
Figure 16 shows the comparison of the compensated output
impedance and uncompensated output impedance varying
with temperature.
0.0006
0.0007
0.0008
0.0009
0.001
0.0011
0.0012
0.0013
25 45 65 85 105
Celsius
Ohm
Zout
Zout(uncomp)
Figure 16. Z
out
vs. Temperature
IMON for Current Monitor
Since VDRP signal reflects the current information of all
phases. It can be fed into the IMON amplifier for current
monitoring as shown in Figure 17. IMON amplifier has a
fixed gain of 2 with an offset when VDRP is equal to 1.3 V,
the internal floating reference voltage. The IMON
amplifier wil l be saturated at an maximum output of 1.09 V
theref ore the total gai n of current should be carefully
considered to make the maximum load c urrent i ndicated by
the IMON output. Figure 18 shows a typical of the relation
betwee n IMON output and the load current.
+
I1
I2
I3
I4
Ilim
Acssum Adrp
OCP
event
+
--
+
--
RISO1
RISO2
RT2
RSUM
RNOR
+
--
Imon
Figure 17. IMON Circuit
Gain = 2
Vimon vs. Iout
0
0.21
0.42
0.63
0.84
1.05
0 102030405060708090100
Iout--A
Vimon--V
Figure 18. IMON Output vs. Output Current
Power Saving Indicator (PSI) and Phase Shedding
VR11.1 requires the processor to provide an output
signal to the VR controller to indicate when the processor
is in a low power state. NCP5392Q use the status of PSI pin
to decide if there is a need to change its operating state to
maximize efficiency at light loads. When PSI = 0, the PSI
function will be enabled, and VR system will be running at
a single phase power saving mode.
The PSI signal will de--assert 1 ms prior to moving to a
normal power state.
NCP5392Q
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26
When system switches on PSI function, a phase shedding
will be presented. Only one is active in the e mulation mode
while other phases are shed. Figure 19 indicates a PSI--on
transition from a 3 --phase mode to a single phase mode.
While staying stable in PSI mode, the PWM signal of phase
1 will vary from a low--state level to high level while other
phases all go to mid--state level (1.5 V typical). Vice verse,
when PSI signal goes high, the system will go back to the
original phase mode such as shown in Figure 20.
Figure 19. PSI turns on, CH1: PWM1, CH2: PWM2,
CH3: PWM3, CH4: PSI
Figure 20. PSI turns off, CH1: PWM1, CH2: PWM2,
CH3: PWM3, CH4: PSI
Auto --PSI Function:
In Auto--PSI mode (APSI_EN=1, PSI=1), the device will
monitor VID lines for transition into/out--of Low Power
States. Figures 21 and 22 describe the Auto--PSI function
during VID transitions.
Figure 21. 10 A Load, VID Down, into PSI, CH1:
PWM1, CH2: PWM2, CH3: PWM3, CH4: VOUT
Figure 22. 10 A Load, VID Up, Out of PSI, CH1: PWM1,
CH2: PWM2, CH3: PWM3, CH4: VOUT
NCP5392Q
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27
OVP Improved Performance
The ove rvoltage protection threshold is not adjustable.
OVP protecti on is e nabled as soon as soft--start begins and
is disabled when part is di sa bled. When OVP is tripped, the
controller com mands all four gate drivers to enable their
low side MOSFETs and VR_RDY transitions low. In order
to recover from an OVP condition, V
CC
must fall below the
UVLO t hreshold. See the state diagram for further details.
The OVP circuit monitors the output of DIFFOUT. If the
DIFFOUT signal reaches 180 mV (typical) above the
nominal 1.3 V offset the OVP will trip and VRRDY will be
pulled low, after eight consecutive OVP events are
dete cted, all PWMs will be latched. The DIFFOUT signal
is the differenc e between the output voltage and the DAC
voltage (mi nus 19 mV if in VR11.1 modes) plus the 1.3 V
internal offset. This resultsin the OVP trackingon the DAC
voltage even during a dynamic change in the VID setting
during operation.
Figure 23. VR11.1, 1.6 V OVP Event
Gate Driver and MOSFET Selection
ON Semiconductor provides the NCP5359 as a
compa nion gate driver IC. The NCP5359 driver is
optimized to work with a range of MOSFETs commonly
used in CPU applications. The NCP5359 provides special
functionality including power saving mode operation and
is required for high performance dynamic VID operation.
Contac t your local ON Semiconductor applications
engine er for MOSFET recommendations.
Board Stackup and Board Layout
Close attention should be paid to the routing of the sense
traces and control lines that propagate away from the
controller IC. Routing should follow the demo board
example. For further information or layout review contact
ON Semiconductor.

NCP5392QMNR2G

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
IC REG CTRLR VR11 4OUT 40QFN
Lifecycle:
New from this manufacturer.
Delivery:
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