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NCP1651DR2

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NCP1651
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13
THEORY OF OPERATION
Introduction
Optimizing the power factor of units operating off of AC
lines is becoming more and more important. There are a
number of reasons for this.
There are a growing number of government regulations
requiring Power Factor Correction PFC. Many of these are
originating in Europe. Regulations such as IEC1000-3-2
are forcing equipment to utilize input stages with topologies
other than a simple off-line front end which contains a
bridge rectifier and capacitor.
There are also system requirements that dictate the use of
PFC. In order to obtain the maximum power from an
existing circuit in a building, the power factor is very critical.
The real power available from such a circuit is:
P
real
+ V
rms
I
rms
PF
A typical off-line converter will have a power factor of
0.5 to 0.6, which means that for a given circuit breaker rating
only 50% to 60% of the maximum power is available. If the
power factor is increased to unity, the maximum available
power can be obtained.
There is a similar situation in aircraft systems, where a
limited supply of power is available from the on-board
generators. Increasing the power factor will increase the
load on the aircraft without the need for a larger generator.
Figure 25. Voltage and Current Waveforms
v, i
v, i
OFF-LINE CONVERTER
PFC CONVERTER
t
t
V
V
I
I
Unity power factor is defined as the current waveform
being in phase with the voltage, and undistorted. Therefore,
there are two causes of power factor degradation – phase
shift and distortion. Phase shift is normally caused by
reactive loads such as motors which are inductive, or
electroluminescent lighting which is highly capacitive. In
such a case the power factor is relatively simple to analyze,
and is determined by the phase shift.
PF + cos
Where is the phase angle between the voltage and the
current.
Reduced power factor due to distortion is more
complicated to analyze and is normally measured with AC
analyzers, although most circuit simulation programs can
also calculate power factor. One of the major causes of
distortion is rectification of the line into a capacitive filter.
This causes current spikes that do not follow the input
voltage waveform. An example of this type of waveform is
shown in the upper diagram in Figure 25.
A power converter with PFC forces the current to follow
the input waveform. This reduces the peak current, the rms
current and eliminates any phase shift.
In most modern PFC circuits, to lower the input current
harmonics, and improve the input power factor, designers
have historically used a boost topology. The boost topology
can operate in the Continuous (CCM), Discontinuous
(DCM), or Critical Conduction Mode.
Most PFC applications using the boost topology are
designed to use the universal input ac power 85-265 Vac, 50
or 60 Hz, and provide a regulated DC bus (typically
400 Vdc). In most applications, the load can not operate off
the high voltage DC bus, so a DC-DC converter is used to
provide isolation between the AC source and load, and
provide a low voltage output. The advantages to this system
configuration are, low THD, a power factor close to unity,
excellent voltage regulation, and transient response on the
isolated DC output. The major disadvantage of the boost
topology is that two power stages are required which lowers
the systems efficiency, increases components count, cost,
and increases the size of the power supply.
ON Semiconductor's NCP1651 offers a unique
alternative for Power Factor Correction designs, where the
NCP1651 has been designed to control a PFC circuit
operating in a flyback topology. There are several major
advantages to using the flyback topology. First, the user can
create a low voltage isolated secondary output, with a single
power stage, and still achieve a low input current distortion,
and a power factor close to unity. A second advantage,
compared to the boost topology with a DC-DC converter, is
a lower component count which reduces the size and the cost
of the power supply.
The NCP1651 can operate in either the Continuous or
Discontinuous Mode of operation, the following analysis
will help to highlight the advantages of Continuous versus
Discontinuous Mode of operation.
NCP1651
http://onsemi.com
14
If we look at a single application and compare the results.
P
O
= 90 watts
Vin = 85-265 V
rms
(analyzed at 85 V
rms
input)
Efficiency = 80%
P
in
= 108 W
V
O
= 48 Vdc
Freq = 100 kHz
Transformer turns ration N = 4
Continuous Mode (CCM)
To force the inductor current to be continuous over the
majority of the input voltage range (85-265 Vac), L
P
needs
to be at least 1 mH. Figure 26 shows the typical current
through the windings of the flyback transformer. During
switch on period, this current flows in the primary and
during the switch off time it flows in the secondary.
TIME
I
PK
I
avg
Figure 26.
The peak current is:
I
PK
= I
avg
+ ((1.414 ⋅ V
in
sin ⋅ t
on
⋅ 2)/L
P
)
where I
avg
= 1.414 ⋅ P
in
/V
in
sin
T
on
= T/((N
S
/N
P
⋅ 1.414 ⋅ V
in
sin /V
O
) +1)
T
on
= 6.19 s
I
PK
= (1.414 ⋅ 113)/85 sin + (1.414 ⋅ 85 ⋅ 6.15 s ⋅ 2) /1mH
= 3.35 A
Discontinuous Mode (DCM)
In the discontinuous mode of operation, the inductor
current falls to zero prior to the end of the switching period
as shown in Figure 27.
TIME
I
PK
I
avg
Figure 27.
To ensure DCM, LP needs to be reduced to approximately
100 H.
I
PK
= (V
in
sin ⋅ 1.414 ⋅ t
on
)/L
P
I
PK
= 1.414 ⋅ 85 sin 90 ⋅ 5.18 s/100 H = 6.23 A
The results show that the peak current for a flyback
converter operating in the Continuous Conduction Mode is
one half the peak current of a flyback converter operating in
the Discontinuous Conduction Mode.
Continuous Conduction Mode
A second result of running in DCM can be higher input
current distortion, EMI, and a lower Power Factor, in
comparison to CCM. While the higher peak current can be
filtered to produce the same performance result, it will
require a larger filter.
A simple Fast Fourier Transform (FFT) was run in Spice
to provide a comparison between the harmonic current
levels for CCM and DCM. The harmonic current levels will
affect the size of the input EMI filter which in some
applications are required to meet the levels of C.I.S.P.R. In
the SPICE FFT model we did not add any front end filtering
so the result of the analysis could be compared directly.
Figure 28. Continuous Conduction Mode
300
250
200
150
100
50
0
(mA)
FREQUENCY (MHz)
0.40.2 0.80.6 1.21.0 1.61.4 2.01.8
At the 100 kHz switching frequency, the rms value from
the FFT is 260 mA, and the 2nd harmonic (200 kHz) is
55mA rms.
Figure 29. Discontinuous Conduction Mode
2.8
2.0
1.6
1.2
0.8
0.4
0
(A)
FREQUENCY (MHz)
0.40.2 0.80.6 1.21.0 1.61.4 2.01.8
2.4
At 100 kHz the rms value from the FFT are 2.8 A, and the
2nd harmonic (200 kHz) is 500mA rms.
NCP1651
http://onsemi.com
15
Results
It is clear from the result of our analysis that a flyback PFC
converter operating in CCM has half the peak current and
one tenth the fundamental (100 kHz) harmonic current
compared to a flyback PFC converter operating in DCM.
The results are lower conduction losses in the MOSFET, and
secondary rectifying diode, and a smaller input EMI filter if
the designer needs to meet the requirements C.I.S.P.R.
conducted emission levels. On the down side to CCM
operation, the flyback transformer will be larger because of
the required higher primary inductance.
The advantages to operating in DCM include lower
switching losses because the current falls to zero prior to the
next switching cycle, and smaller transformer size.
It will ultimately be up to the designer to perform a
trade-off study to determine which topology, Boost versus
Flyback, Continuous versus Discontinuous Mode of
operation will meet all the system performance
requirements. But the recent introduction of the NCP1651
allows the system designer one additional option.
For an average current mode flyback topology based PFC
converter, determining the transformer parameters (primary
inductance and turns ratio) involves several trade-offs.
These include peak-to-average current ratio (higher
inductance or turns ratio result in lower peak current),
switching losses (higher turns ratio leads to higher peak
voltage and higher switching losses), CCM vs. DCM
operation (lower values of turns ratio or higher values of
inductance extend the CCM range) and range of duty cycles
over the operational line and load range. ON Semiconductor
has designed an Excel-based spreadsheet to help design
with the NCP1651 and balance these trade-offs. The design
aid is downloadable free-of-charge from our website
(www.onsemi.com).
The ideal solution depends on the specific application
requirements and the relative priority between factors such
as THD performance, cost, size and efficiency. The design
aid allows the designer to consider different scenarios and
settle on the best solution foe a given application. Following
guidelines will help in settling towards the most feasible
solution.
1. Turns Ratio Limitations: While higher turns ratio
can limit the reflected primary voltage and current,
it is constrained by the inherent limitations of the
flyback topology. A turns ratio of higher than 20:1
will result in very high leakage inductance and
lead to high leakage spikes on the primary switch.
Thus, practical application of this approach is
restricted to output voltages 12 V and above.
2. CCM Operation: The NCP1651 is designed to
operate in both CCM and DCM modes. However,
the CCM operation results in much better THD
than the DCM operation. Thus, it is recommended
that the circuit be designed to operate in CCM at
the specified test condition for harmonics
compliance (typically at 230 V, full load). Please
keep in mind that at or near zero crossing
(<10 deg angle), it is neither necessary nor feasible
to maintain CCM operation.
3. Following key governing equations have been
incorporated in the design aid:
PFC Operation
The basic PWM function of the NCP1651 is controlled by
a small block of circuitry, which comprises the DC
regulation loop and the PFC circuit. These components are
shown in Figure 30.
There are three inputs to this loop. They are the fullwave
rectified sinewave, the instantaneous input current and the
error signal at the FB/SD pin.
The input current is forced to maintain a near unity power
factor due to the control of the AC error amplifier. This
amplifier uses information from the AC input voltage and
the AC input current to control the power switch in a manner
that gives good DC regulation as well as excellent power
factor.
The reference multiplier sets a reference level for the input
fullwave rectified sinewave. One of its inputs is connected
to a scaled down fullwave rectified sinewave, and the other
receives the error signal which has been converted to a
current. The error signal adjusts the level of the fullwave
rectified sinewave on the multiplier's output without
distorting it. To accomplish this, it is necessary for the
bandwidth of the DC error amp to be less than twice the
lowest line frequency. Typically it is set at a factor of ten less
than the rectified frequency (e.g. for a 60 Hz input, the
bandwidth would be 12 Hz).
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NCP1651DR2

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Manufacturer:
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Description:
Power Factor Correction - PFC Single Stage PFC
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