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NCP1651DR2

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NCP1651
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25
Basic Specifications
The design of any power converter begins with a basic set
of specifications. The following parameters should be
known before you begin:
Po
max
(Maximum rated output power)
Vrms
min
(Minimum operational line voltage)
Vrms
max
(Maximum operational line voltage)
f
switch
(Nominal switching frequency)
V
out
(Nominal regulated output voltage)
Most of these parameters will be dictated by system
requirements.
Transformer
For an average current mode, fixed frequency PFC
converter, there is no magic formula to determine the
optimum value of the transformer's primary inductance.
There are several trade-offs that should be considered.
These include peak current vs. average current, switching
losses vs. core losses and range of duty cycles over the
operational line and load range. All of these are a function
of inductance, line and load. These parameters determine
when the converter is operating in the continuous
conduction mode and when it is operating in the
discontinuous conduction mode.
If you are designing your own transformer, the
ONSemiconductor spreadsheet (NCP1651_Design.xls)
that is available as a design aid for this part can be of help.
Enter various values of inductance as well as the turns ratio
and observe the variation in duty cycle and peak current vs.
average current.
The transformer's duty cycle is an important parameter.
There are two main limitations for the duty cycle. The first
is the output voltage reflected back to the primary, which is
scaled by the turns ratio. This means that with a 10:1
(pri:sec) turns ratio, and a 12 volt output, the power switch
will see the input voltage plus 120 volts (10 x 12 volts) plus
leakage inductance spike. This reflected voltage determines
the maximum voltage rating of the power switch.
The second, there are practical limits to the turns ratio.
Given the flyback converter transfer function, continuous
conduction mode,
V
O
+ V
in
n(Dń1 * D)
It is evident that there is a direct relationship between duty
cycle and the turns ratio. In general, 10:1 is about the
maximum, although some transformer manufacturers go as
high as 12:1 or even 15:1. Turns ratios of 20:1 and above are
not normally practical as they result in very high values of
leakage inductance, which creates large spikes on the power
switch. They also have a very large reflectovoltage
associated with them.
The other option is to contact a transformer manufacturer
such as Coiltronics (www.cooperet.com/
) or Coilcraft
(www.coilcraft.com/
). These companies will design and
manufacture transformers to your requirements.
Using the available spreadsheet, with the following
parameters, a primary inductance of 330 H and a turns ratio
of 10:1 would be a good choice.
Limits
Po
max
= 100 W
Vin
max
= 265 V
rms
Vin
min
= 85 V
rms
V
O
= 12 V
L
P
= 330 H
f
switch
= 100 kHz
N
p
/N
s
= 10
Figure 39. Switching Current versus Phase Angle
PHASE ANGLE (°)
0 45 90 135 180
CURRENT (A)
6
5
4
3
2
1
0
PEAK CURRENT
PEDESTAL
CURRENT
Figure 40. Continuous/Discontinuous and Duty Cycle
DEGREES (°)
0 45 90 135 180
DUTY CYCLE (%)
100
75
50
25
0
100% = Discontinuous
50% = Continuous
DUTY CYCLE
MODE
If an auxiliary winding is desired to provide a bias supply,
it should provide a minimum of 12.1 volts (to exceed the
UVLO spec) and a maximum of 18 volts. The auxiliary
winding should be connected such that it conducts when the
power switch is off. Near the zero crossings of the line
frequency, the voltage will have a peak voltage equal to the
regulated output voltage divided by the turns ratio. The filter
cap on the V
CC
pin needs to be of sufficient size to hold the
voltage up over between the zero crossings.
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Error Amplifier
The error amplifier resides on the secondary side of the
circuit, and therefore is not part of the chip. A minimal
solution would include either a discrete amplifier and
reference, or an integrated circuit that combines both, such
as the TL431 series of regulators.
Figure 41. Error Amplifier Circuit
-
+
FB/SD
Error
Amp
R
fb
C
fb
R
dc2
R
dc1
R
opto
V′
V
out
V
ref2
This configuration for the error amplifier will result in a
low cost regulator, however, due to the slow loop response
of a PFC regulator it will not protect against overvoltage
conditions (e.g. load removal) or droop when a transient
load is added.
The primary side circuit has been designed such that the
PFC controller will operate at maximum duty cycle with the
optocouple in a non-conducting state. This is necessary to
allow the unit to bring up the output when the system is
initially energized. At this time there is not output voltage
available to drive the LED in the optocoupler.
In the circuit of Figure 41, the amplifier and reference
need to be rated at the maximum voltage that the output will
experience, including transient conditions. Resistors R
dc1
and R
dc2
need to be chosen such that the voltage at V′ is
equal to V
ref2
when V
out
is at its regulated voltage. R
opto
is
a current limiting resistor that protects the optocoupler from
current transients due to output surges.
This design also includes inherent compensation from
transients. Since the bandwidth of the error amplifier is very
low, its output can not respond rapidly to changes in the
output voltage. A transient change in the output voltage will
change the current through R
opto
. Since the output of the
error amplifier does not change immediately, if the output
voltage increases, the voltage across R
opto
will increase.
This drives more current through the optocoupler, which in
turn reduces the output of the converter.
An alternate regulator is recommended, which is only
slightly more expensive, and offers excellent protection
from positive transients, and quick recovery from negative
transients.
Figure 42. Error Amp with Over/Undershoot
Protection
-
+
-
+
-
+
12 V
7.5 k
R
bias
0.01 F
4.02 k
5.23 k
9.31 k
R
out
453
422
5.23 k
R
tn
Undervoltage
Capacitor
3.6 k
R
opto
C
out
Error Amplifier
MC3303
Overvoltage
Comparator
TL431
The configuration shown in Figure 42, incorporates an
error amplifier with slow loop response, plus overvoltage
and undervoltage comparators. Under normal operation the
outputs of the Undervoltage and Overvoltage Comparators
are high. The Undervoltage Comparator provides drive for
the optocoupler, while the Overvoltage Comparator reverse
biases the diode on its output and is out of the loop.
This circuit is designed with 8% trip points both above and
below the regulation limit. If an overvoltage condition
exists, the Overvoltage comparator will respond very
quickly. When its output goes low, it will provide maximum
drive to the optocoupler, which will shut off the output of the
converter.
If the output voltage drops 8% or more below its regulated
level, the Undervoltage Comparator will go low. This will
remove the drive from the optocoupler, which will allow the
regulator to increase the duty cycle and return the output to
its regulation range much faster than the error amplifier
could.
This configuration will work over a range of 5 to 30 volts,
with the appropriate changes in R
out
, R
bias
and R
opto
.
R
out
(k) = (V
out
- 4.753) / 0.7785
R
bias
(k) = (V
out
- 4.4)
R
opto
(k) = (V
out
- 3) / 2
The value for R
opto
will allow a maximum of 2 mA to
drive the optocoupler. If additional current is needed, change
the 2 in the denominator of that equation to the current
(inmA) that is desired.
NCP1651
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27
AC Voltage Divider
The voltage divider from the input rectifiers to ground is
a simple but important calculation. For this calculation it is
necessary to know the maximum line that the unit can
operate at. The peak input voltage will be:
Vin
peak
= 1.414 x Vrms
max
The maximum voltage at the AC input (pin 5) is 3.75 volts
(this is true for both multipliers).
If the maximum line voltage is 265 Vac, the peak input
voltage is:
Vin
peak
= 1.414 x 265 V
rms
= 375 V
pk
To keep the power dissipation reasonable for a 1/2 watt
resistor (R
ac1
), it should dissipate no more than 1/4 watt. The
power in this resistor is:
PR
ac1
= (375 V - 3.75 V)
2
/ R
ac1
= 0.25 watts
so: R
ac1
= 551 k
To minimize dissipation, use the next largest standard value,
or 560 k.
Typically, two 1/4 resistors are used in series to handle the
power.
Then, R
ac2
= 3.75 V / ((375 V - 3.75 V) / 560 k) = 5.6 k
Current Sense Resistor/Ramp Compensation
The combination of the voltage developed across the
current sense resistor and ramp compensation signal, will
determine the peak instantaneous current that the power
switch will be allowed to conduct before it is turned off.
The vector sum of the three signals that combine to create
the signal at the non-inverting input to the PWM comparator
must add up to 4.0 volts in order to terminate the switch
cycle. These signals are the error signal from the AC error
amp, the ramp compensation signal, and the instantaneous
current. For a worst case condition, the output of the AC
error amp could be zero (current), which would require that
the sum of the ramp compensation signal and current signal
be 4.0 volts. This must be evaluated under full load and low
line conditions.
For proper ramp compensation, the ramp signal should
match the falling di/dt (which has been converted to a dv/dt)
of the inductor at 50% duty cycle. 50% duty cycle will occur
when the input voltage is 50% of the output voltage. Both the
falling di/dt and output voltage need to be reflected by the
transformer turns ratio to the primary side. Thus the
following equations for R
S
and R
RC
must be satisfied:
di/dt primary = V
in
/L
P
⋅ T/2
di/dt secondary = V
O
/L
S
⋅ T/2
L
S
+
ǒ
N
S
N
P
Ǔ
2
L
P
di/dt reflected to the primary:
ǒ
V
O
L
P
Ǔǒ
N
P
N
S
Ǔ
2
@
T
2
@
N
S
N
P
Simplifies to:
V
O
/L
P
⋅ N
P
/N
S
⋅ T/2
di/dt primary = di/dt secondary
V
in
/L
P
⋅ T/2 = V
O
/L
P
⋅ N
P
/N
S
⋅ T/2
V
in
/L
P
= V
O
/L
P
⋅ N
P
/N
S
Equation 2)
For proper slope compensation, the relationship between
R
S
and R
RC
is:
di/dt (primary) ⋅ T ⋅ R
S
⋅ High Frequency Current Gain =
V
Rcomp
V
O
/L
P
⋅ T ⋅ N
P
/N
S
⋅ R
S
⋅ 16 k/3 k = 102.4 k/R
RC
R
S
= (19,200/R
RC
⋅ T) ⋅ (L
P
/V
O
) ⋅ (N
S
/N
P
)
Equation 3)
t
on
= T/(N
S
/N
P
⋅ (√2 ⋅ V
LL
/V
O
)) + 1
For maximum output current, when the error amplifier is
saturated in a low state, the ramp compensation signal plus
the current signal must equal 4.0 volts (3.8 volts is used to
avoid over driving the amplifier), which is the reference
level for the PWM comparator. So:
Equation 4) Vref
PWM
= Vin
ST
+ V
Rcomp
3.8 V = I
PK
⋅ R
S
⋅ 16 k/3 k + 102.4 k/R
RC
⋅ t
on
/T
R
RC
+
102.4kt
on
(3.8 * 5.3I
PK
R
S
)
Combining equations 2 and 4 gives:
R
S
+
3.8
N
P
N
S
t
on
V
O
0.1875L
P
) 5.33I
pk
Where:
R
S
is the current shunt resistor (Ohms)
R
RC
is the ramp compensation resistor (Ohms)
t
on
is the on time for the conditions given (s)
T is the period for the switching frequency (s)
L
P
is the primary inductance of the transformer (H)
V
out
is the output voltage (VDC)
V
rms
is the rms line voltage at low line (V
rms
)
P
out
is the output power at full load (watts)
I
avg
(T) is the average current for one switching cycle (A)
I
pk
is the instantaneous peak primary side current (A)
V
(t)
is the peak line voltage (volts)
N
P
/N
S
is the transformer turns ratio (dimensionless)
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NCP1651DR2

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Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC Single Stage PFC
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