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28
Current Scaling Resistor & Filter Capacitor
R
7
sets the gain of the averaged current signal out of the
current sense amplifier which is fed into the AC error
amplifier. R
7
is used to scale the current to the appropriate
level for protection purposes in the AC error amplifier
circuit.
R
7
should be calculated to limit the maximum current
signal at the input to the AC error amplifier to less than
4.5volts at low line and full load. 4.5 volts is the clamp
voltage at the output of the reference amplifier and limits the
maximum averaged current that the unit can process. The
equation for R
7
is:
R
7
+
212k @ R
S
@ P
in
Vin
LL
ǒ
4.5 * (0.75 @ AC
ratio
@ Vin
LL
@ 2
Ǹ
)
Ǔ
Where: P
in
= rated input power (W)
Where: R
S
= Shunt resistance (W)
Where: V
inLL
= min. operating rms input voltage (W)
Where: AC
ratio
= AC attenuation factor at pin 9
This equation does not allow for tolerances, and it would
be advisable to increase the input power to assure operation
at maximum power over production tolerance variations.
The current sense filter capacitor should be selected to set
its pole about a factor of 10 below the switching frequency.
C
6
+
5.3
f
Where: C
6
= Pin 6 capacitance (nF)
Where: f = pole frequency (kHz)
so, for a 100 kHz switching frequency, a 10 kHz pole is
desirable, and C
6
would be 0.5 nF.
Reference Multiplier
The output of the reference multiplier is a pulse width
modulated representation of the analog input. The multiplier
is internally loaded with a resistor to ground which will set
the DC gain. An external capacitor is required to filter the
signal back into one that resembles the input fullwave
rectified sinewave. The pole for this circuit should be greater
than the line frequency and lower than the switching
frequency.
1/15th of the switching frequency is a recommended
starting value for a 60 Hz line frequency. The filter capacitor
for pin 10 can be determined by the following equation:
C
10
+
1
23.1425kf
pole
+
6.366E-6
f
pole
Where: C
10
= Pin 10 capacitance (F)
Where: f
pole
= Ref gain pole freq (Hz)
AC Error Amplifier
The AC error amplifier is a transconductance amplifier
that is terminated with a series R
C
impedance. This creates
a pole-zero pair.
To determine the values of R
3
and C
3
, it is necessary to
look at the two signals that reach the PWM inputs. The
non-inverting input is a slow loop using the averaged
current signal. It's gain is:
A
If
+
30k
3k
@
15k
R
7
@ (g
m
@ R
11
) @ 2.3
Where the first two terms are the gains in the current sense
amplifier averaging circuit. The next term is the gain of the
transconductance amplifier and the constant is the gain of
the AC Reference Buffer.
The high frequency path is that of the instantaneous
current signal to the PWM non-inverting input. This gain is
16 k/3 k = 5.33, since the input signal is converted to a
current through a 3 k resistor in the current sense amplifier,
and then terminated by the 16k resistor at the PWM input.
For stability, the gain of the low frequency path must be
less than the gain of the high frequency path. This can be
written as:
345, 000 @
g
m @ R
11
R
7
t 5.3
The suggested resistor and capacitor values are:
R
11
+
R
7
130,000 g
m
and for a zero at 1/10th of the switching frequency
C
11
+
1.59
f
SW
R
11
Where: R
7
& R
11
are in units of Ohms
Where: g
m
is in units of mhos
Where: C
11
is in Farads
Where: f
sw
is in Hz
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Loop Compensation
Figure 43. Voltage Regulation Loop
-
+
REFERENCE
MULTIPLIER
PWM
OUT
1
LOGIC
V
ref2
4 V
I
S+
Q1
5
C.S. Amp
-
+
25 k
AC
ERROR
AMP
R
S
R
7
7I
avg
V
ref
DIVIDER ERROR AMP REFERENCE SIGNAL MODULATOR AND OUTPUT STAGE
VȀ
V
o
+
R
dc2
R
dc1
) R
dc2
f
z
+
1
2C
fb
R
fb
A
v
+
1
2fC
fb
R
dc1
V
ref
V
fb
+ 2.66V
ac
V
ac
+
V
line
R
ac2
R
ac1
) R
ac2
V
out
I
in
+
ǒ
N
p
N
s
Ǔ
R
L
ǒ
T * t
on
t
on
Ǔ
R
dc1
R
dc2
f
p
+
1
2R
L
C
R
ac1
R
L
C
V
o
V
ac
V
V
line
I
in
N
p
: N
s
R
ac2
C
10
10Ref Fltr-
+
R
opto
R
fb
C
fb
ERROR
AMP
V
ea
0.022 F
C
8
6.5 V
3.8 k
OPTO TRANSFER
V
fb
V
ea
+
3.8kCTR
R
opto
A
v
+ R
fb
ńR
dc1
for f > f
z
:
for f < f
z
:
I
in
V
ref
+
R
7
R
S
75, 000
V
fb
FB/SD
8
Loop Model
The model for the voltage loop has been broken down into
six sections. The voltage divider, error amplifier, and opto
Transfer are external to the chip, and the reference signal,
modulator and output stage are internal.
The modulator and output stage circuitry is greatly
simplified based on the assumption that that poles and zeros
in the current feedback loop are considerably greater than
the bandwidth of the overall loop. This should be a good
assumption, because a bandwidth in the kilohertz is
necessary for a good current waveform, and the voltage error
amplifier needs to have a bandwidth of less than the lowest
line frequency that will be used.
There are two poles in this circuit. The output filter has a
pole that varies with the load. The pole on the voltage error
amplifier will be determined by this analysis.
Voltage Divider
The voltage divider is located on the secondary side
circuitry. It is a simple resistive divider that reduces the
output voltage to the level required by the internal reference
on the voltage error amplifier. If the amplifier circuit of
Figure 42 is used, there are four resistors instead of 2. To
determine the gain of this circuit, R
dc1
is the equivalent of
the upper two resistors, 9.31 k and 453 Ohms respectively,
and R
dc2
is the equivalent of the lower two resistors, 422 and
5.23 k respectively.
Voltage Error Amplifier
The voltage error amplifier is constrained by the two
equations. When this amplifier is compensated with a
pole-zero pair, there will be a unity gain pole which will be
cancelled by the zero at frequency f
z
. The corresponding
bode plot would be:
Figure 44. Pole-zero Bode Plot
f, FREQUENCY
GAIN (dB)
20
0
-20
Unity Gain
A
V
f
z
The gain at frequencies greater than f
z
is determined by
R
fb
. Once R
fb
is determined, the value of C
fb
can be easily
calculated using the formula for f
z
.
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Optocoupler Transfer
The optocoupler is used to allow for galvanic isolation for
the error signal from the secondary to primary side circuits.
The gain is based on the Current Transfer Ratio of the
device. This can change over temperature and time, but will
not result in a large change in dB.
The recommended capacitor at pin 8 is 0.022 F. If a larger
capacitor is used, the pole may become low enough that it
will have an effect on the gain phase plots near the unity gain
crossover frequency. In this case and additional zero will be
required in the error amplifier bias circuitry.
Reference Signal
The error signal is transmitted to the primary side circuit
via. the optocoupler, is converted to a current by the V-I
converter and is then used as an input to the reference
multiplier. The gain of this block is dependent on the AC
input voltage, because of the multiplier which requires two
inputs for one output.
Modulator and Output Stage
The modulator receives an input from the reference
multiplier and forces the current to follow the shape and
amplitude. The is an internal loop within this section due to
the current sense amplifier. Based on the assumptions listed
in the introduction to this analysis, this is not analyzed
separately.
The equation for the gain is good for frequencies below
the pole. There is a single pole due to the output filter. Since
the NCP1651 is a current mode converter, the inductor is not
part of the output pole as can be seen in that equation.
The modulator and output stage transfer functions have
been split into two sets of equations. The first defines the
relationship between the input current and AC reference
signal, and the later, define the output stage gain and pole.
Due to the nature of a flyback transformer, the gain of the
output stage is dependant on the duty cycle (t
on
/T). For
continuous mode operation, the on-time is:
t
on
+
T
N
S
N
P
@
2
Ǹ
@
V
rms
V
out
) 1
Calculating the Loop Gain
At this point in the design process, all of the parameters
involved in this calculation have been determined with the
exception of the pole-zero pair on the output of the voltage
error amplifier.
All equations give gains in absolute numbers. It is
necessary to convert these to the decibel format using the
following formula:
A(dB) = 20 Log
10
(A)
For example, the voltage divider would be:
A +
5.6k
560k ) 5.6k
+ 0.0099
A(dB) = 20 Log
10
0.0099 = -40 dB
The gain of the loop will vary as the input voltage changes.
It is recommended that the compensation for the error
amplifier be calculated under high line, full load conditions.
This should be the greatest bandwidth that the unit will see.
By necessity, the unity gain (0 dB) loop bandwidth for a
PFC unit, must be less than the line frequency. If the
bandwidth approaches or exceeds the line frequency, the
voltage error amplifier signal will have frequency
components in its output that are greater than the line
frequency. These components will cause distortion in the
output of the reference amplifier, which is used to shape the
current waveform. This in turn will cause distortion in the
current and reduce the power factor.
Typically the maximum bandwidth for a 60 Hz PFC
converter is 10 Hz, and slightly less for a 50 Hz system. This
can be adjusted to meet the particular requirements of a system.
The unity gain bandwidth is determined by the frequency at
which the loop gain passes through the 0dB level.
For stability purposes, the gain should pass through 0dB
with a slope of -20 dB for approximately on decade on either
side of the unity gain frequency. This assures a phase margin
of greater than 45°.
The gain can be calculated graphically using the equations
of Figure 18 as follows:
Divider:
Calculate V/V
o
in dB, this value is constant so it
will not change with frequency.
Optocoupler Transfer:
Calculate V
fb
/V
ea
using the equation
provided. Convert this value into dB.
Reference Signal:
Calculate V
ref
/V
fb
using the peak level of
the AC input signal at high line that will be seen on pin 9.
Convert this to dB. This is also a constant value.
Modulator and Output Stage:
Calculate the gain in dB for
DI
o
/DV
ref
for the modulator, and also the gain in dB for the
output stage (DV
out
/DI
in
). Calculate the pole frequency. The
gain will be constant for all frequencies less than f
p
. Starting
at the pole frequency, this gain will drop off at a rate of
20dB/decade.
Plot the sum of all of the calculated values. Be sure to
include the output pole. It should resemble the plot of
Figure45. This plot shows a gain of 34 dB until the pole of
the output filter is reached at 3 Hz. After that, the gain is
reduced at a rate of 20 dB/decade.

NCP1651DR2

Mfr. #:
Manufacturer:
ON Semiconductor
Description:
Power Factor Correction - PFC Single Stage PFC
Lifecycle:
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