DS12CR887-5+ Datasheet DS12CR887-33+, DS12CR887-5+, DS12R885S-33+ | P10-P12

DS12R885/DS12CR887/DS12R887

RTCs with Constant-Voltage Trickle Charger

10 ____________________________________________________________________

Pin Description (continued)

SO EDIP

BGA

NAME FUNCTION

12, 16 12

D5–D8,

E1–E8,

F5–F8

GND Ground

13 13 C1 CS

Chip-Select Input. The active-low chip-select signal must be asserted low for a bus cycle

in the DS12R885 to be accessed. CS must be kept in the active state during DS and AS

for Motorola timing and during DS and R/W for Intel timing. Bus cycles that take place

without asserting CS latch addresses, but no access occurs. When V

is below V

volts,

the DS12R885 inhibits access by internally disabling the CS input. This action protects the

RTC data and the RAM data during power outages.

14 14 C3 AS

Address Strobe Input. A positive-going address-strobe pulse serves to demultiplex the

bus. The falling edge of AS causes the address to be latched within the DS12R885. The

next rising edge that occurs on the AS bus clears the address regardless of whether CS is

asserted. An address strobe must immediately precede each write or read access. If a

write or read is performed with CS deasserted, another address strobe must be performed

prior to a read or write access with CS asserted.

15 15 C2 R/W

Read/Write Input. The R/W pin has two modes of operation. When the MOT pin is

connected to V

for Motorola timing, R/W is at a level that indicates whether the current

cycle is a read or write. A read cycle is indicated with a high level on R/W while DS is high.

A write cycle is indicated when R/W is low during DS. When the MOT pin is connected to

GND for Intel timing, the R/W signal is an active-low signal. In this mode, the R/W pin

operates in a similar fashion as the write-enable signal (WE) on generic RAMs. Data are

latched on the rising edge of the signal.

2, 3, 16,

20–22

A3 N.C.

No Connection. This pin should remain unconnected. On the EDIP, these pins are missing

by design.

17 17 A1 DS

Data Strobe or Read Input. The DS pin has two modes of operation depending on the level of

the MOT pin. When the MOT pin is connected to V

, Motorola bus timing is selected. In this

mode, DS is a positive pulse during the latter portion of the bus cycle and is called data

strobe. During read cycles, DS signifies the time that the DS12R885 is to drive the

bidirectional bus. In write cycles, the trailing edge of DS causes the DS12R885 to latch the

written data. When the MOT pin is connected to GND, Intel bus timing is selected. DS

identifies the time period when the DS12R885 drives the bus with read data. In this mode, the

DS pin operates in a similar fashion as the output-enable (OE) signal on a generic RAM.

DS12R885/DS12CR887/DS12R887

RTCs with Constant-Voltage Trickle Charger

____________________________________________________________________ 11

Pin Description (continued)

SO EDIP

BGA

NAME FUNCTION

18 18 A2 RESET

Reset Input. The active-low RESET pin has no effect on the clock, calendar, or RAM. On

power-up, the RESET pin can be held low for a time to allow the power supply to

stabilize. The amount of time that RESET is held low is dependent on the application.

However, if RESET is used on power-up, the time RESET is low should exceed 200ms to

ensure that the internal timer that controls the DS12R885 on power-up has timed out.

When RESET is low and V

is above V

, the following occurs:

A. Periodic interrupt-enable (PIE) bit is cleared to 0.

B. Alarm interrupt-enable (AIE) bit is cleared to 0.

C. Update-ended interrupt-enable (UIE) bit is cleared to 0.

D. Periodic-interrupt flag (PF) bit is cleared to 0.

E. Alarm-interrupt flag (AF) bit is cleared to 0.

F. Update-ended interrupt flag (UF) bit is cleared to 0.

G. Interrupt-request status flag (IRQF) bit is cleared to 0.

H. IRQ pin is in the high-impedance state.

I. The device is not accessible until RESET is returned high.

J. Square-wave output-enable (SQWE) bit is cleared to 0.

In a typical application, RESET can be connected to V

. This connection allows the

DS12R885 to go in and out of power fail without affecting any of the control registers.

19 19 A4 IRQ

Interrupt Request Output. The IRQ pin is an active-low output of the DS12R885 that can

be used as an interrupt input to a processor. The IRQ output remains low as long as the

status bit causing the interrupt is present and the corresponding interrupt-enable bit is

set. The processor program normally reads the C register to clear the IRQ pin. The

RESET pin also clears pending interrupts. When no interrupt conditions are present, the

IRQ level is in the high-impedance state. Multiple interrupting devices can be

connected to an IRQ bus, provided that they are all open drain. The IRQ pin is an open-

drain output and requires an external pullup resistor to V

20 — — V

BACKUP

Connection for Rechargeable Battery or Super Cap. This pin provides trickle charging

when V

is greater than V

BACKUP

. On the DS12CR887 and DS12R887, the V

BACKUP

is missing and is internally connected to a lithium cell.

21 — A5 RCLR

RAM Clear. The active-low RCLR pin is used to clear (set to logic 1) all 114 bytes of

general-purpose RAM, but does not affect the RAM associated with the RTC. To clear

the RAM, RCLR must be forced to an input logic 0 during battery-backup mode when

is not applied. The RCLR function is designed to be used through a human

interface (shorting to ground manually or by a switch) and not to be driven with external

buffers. This pin is internally pulled up. Do not use an external pullup resistor on this

pin.

23 23 C4 SQW

Square-Wave Output. The SQW pin can output a signal from one of 13 taps provided by

the 15 internal divider stages of the RTC. The frequency of the SQW pin can be changed

by programming Register A, as shown in Table 3. The SQW signal can be turned on and

off using the SQWE bit in Register B. The SQW signal is not available when V

is less

than V

24 24

A6–A8,

B1–B8,

C6–C8

DC Power Pin for Primary Power Supply. When VCC is applied within normal limits, the

device is fully accessible and data can be written and read. When V

is below V

reads and writes are inhibited.

DS12R885/DS12CR887/DS12R887

RTCs with Constant-Voltage Trickle Charger

12 ____________________________________________________________________

Detailed Description

The DS12R885 is a drop-in replacement for the

DS12885 RTC. The device provides 14 bytes of real-

time clock/calendar, alarm, and control/status registers

and 114 bytes of nonvolatile, battery-backed static

RAM. A time-of-day alarm, three maskable interrupts

with a common interrupt output, and a programmable

square-wave output are available. The DS12R885 also

operates in either 24-hour or 12-hour format with an

AM/PM indicator. A precision temperature-compensat-

ed circuit monitors the status of V

. If a primary

power-supply failure is detected, the device automati-

cally switches to a backup supply. The backup supply

input supports either a rechargeable battery or a super

cap, and includes an integrated trickle charger. The

trickle charger is always enabled. The DS12R885 is

accessed through a multiplexed address/data bus that

supports Intel and Motorola modes.

The DS12R887 is a surface-mount package using the

DS12R885 die, a 32.768kHz crystal, and a recharge-

able battery. The device provides a real-time clock/cal-

endar, one time-of-day alarm, three maskable interrupts

with a common interrupt output, a programmable

square wave, and 114 bytes of nonvolatile, battery-

backed static RAM. The date at the end of the month is

automatically adjusted for months with fewer than 31

days, including correction for leap years. It also oper-

ates in either 24-hour or 12-hour format with an AM/PM

indicator. A precision temperature-compensated circuit

monitors the status of V

. If a primary power failure is

detected, the device automatically switches to a back-

up battery included in the package. The device is

accessed through a multiplexed byte-wide interface,

which supports both Intel and Motorola modes.

The DS12CR887 EDIP integrates a DS12R885 die with

a crystal and battery. The charging circuit on the

DS12R885 die is disabled. The battery has sufficient

capacity to power the oscillator and registers for five

years in the absence of V

at +25°C.

The DS12R887 BGA includes a crystal and a recharge-

able battery. A fully charged battery can power the oscil-

lator and registers (typical current at +25°C) in the

absence of V

for approximately 11 days (10% of

capacity consumed) or 98 days (90% capacity con-

sumed). When the discharge depth is 10% of capacity,

the battery can be recharged up to 1,000 times. If the dis-

charge depth is 90% of capacity, the battery can be

recharged up to 30 times. Thus, the life of the device

would be approximately 30 years (11 days X 1,000

cycles) or 8 years (98 days x 30 cycles). Charging time to

full capacity is approximately two days with V

applied.

Please consult related application notes for detailed

information on battery lifetime versus depth of dis-

charge, and expected product lifetime based upon

battery cycles.

Oscillator Circuit

The DS12R885 uses an external 32.768kHz crystal. The

oscillator circuit does not require any external resistors

or capacitors to operate. Table 1 specifies several crys-

tal parameters for the external crystal. Figure 1 shows a

functional schematic of the oscillator circuit. An enable

bit in the control register controls the oscillator.

Oscillator startup times are highly dependent upon

crystal characteristics, PC board leakage, and layout.

High ESR and excessive capacitive loads are the major

contributors to long startup times. A circuit using a

crystal with the recommended characteristics and

proper layout usually starts within one second.

COUNTDOWN

CHAIN

CRYSTAL

RTC REGISTERS

DS12R885

Figure 1. Oscillator Circuit Showing Internal Bias Network

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal

Frequency

32.768 kHz

Series

Resistance

ESR 50 k

Load

Capacitance

12.5 pF

Table 1. Crystal Specifications*

The crystal, traces, and crystal input pins should be isolated

from RF generating signals. Refer to

Application Note 58:

Crystal Considerations with Dallas Real-Time Clocks (RTCs)

for

additional specifications.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

DS12CR887-5+

Mfr. #:

Buy DS12CR887-5+

Manufacturer:

Maxim Integrated

Description:

Real Time Clock RTC w/Constant V Trickle Charger

Lifecycle:

New from this manufacturer.

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DS12CR887-5+

DS12CR887-5+

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