DS12CR887-5+ Datasheet DS12CR887-33+, DS12CR887-5+, DS12R885S-33+ | P16-P18

DS12R885/DS12CR887/DS12R887

RTCs with Constant-Voltage Trickle Charger

16 ____________________________________________________________________

Bit 7: Update-In-Progress (UIP). This bit is a status

flag that can be monitored. When the UIP bit is a 1, the

update transfer occurs soon. When UIP is a 0, the

update transfer does not occur for at least 244µs. The

time, calendar, and alarm information in RAM is fully

available for access when the UIP bit is 0. The UIP bit is

read-only and is not affected by RESET. Writing the

SET bit in Register B to a 1 inhibits any update transfer

and clears the UIP status bit.

Bits 6, 5, and 4: DV2, DV1, DV0. These three bits are

used to turn the oscillator on or off and to reset the

countdown chain. A pattern of 010 is the only combina-

tion of bits that turn the oscillator on and allow the RTC

to keep time. A pattern of 11x enables the oscillator but

holds the countdown chain in reset. The next update

occurs at 500ms after a pattern of 010 is written to DV0,

DV1, and DV2.

Bits 3 to 0: Rate Selector (RS3, RS2, RS1, RS0).

These four rate-selection bits select one of the 13 taps

on the 15-stage divider or disable the divider output.

The tap selected can be used to generate an output

square wave (SQW pin) and/or a periodic interrupt. The

user can do one of the following:

1) Enable the interrupt with the PIE bit;

2) Enable the SQW output pin with the SQWE bit;

3) Enable both at the same time and the same rate;

4) Enable neither.

Table 3 lists the periodic interrupt rates and the square-

wave frequencies that can be chosen with the RS bits.

These four read/write bits are not affected by RESET.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

UIP DV2 DV1 DV0 RS3 RS2 RS1 RS0

Control Register A

Control Registers

The DS12R885 has four control registers that are

accessible at all times, even during the update cycle.

DS12R885/DS12CR887/DS12R887

____________________________________________________________________ 17

Bit 7: SET. When the SET bit is 0, the update transfer

functions normally by advancing the counts once per

second. When the SET bit is written to 1, any update

transfer is inhibited, and the program can initialize the

time and calendar bytes without an update occurring in

the midst of initializing. Read cycles can be executed in

a similar manner. SET is a read/write bit and is not

affected by RESET or internal functions of the

DS12R885.

Bit 6: Periodic Interrupt Enable (PIE). The PIE bit is a

read/write bit that allows the periodic interrupt flag (PF) bit

in Register C to drive the IRQ pin low. When the PIE bit is

set to 1, periodic interrupts are generated by driving the

IRQ pin low at a rate specified by the RS3–RS0 bits of

being driven by a periodic interrupt, but the PF bit is still

set at the periodic rate. PIE is not modified by any internal

DS12R885 functions, but is cleared to 0 on RESET.

Bit 5: Alarm Interrupt Enable (AIE). This bit is a

read/write bit that, when set to 1, permits the alarm flag

(AF) bit in Register C to assert IRQ. An alarm interrupt

occurs for each second that the three time bytes equal

the three alarm bytes, including a don’t-care alarm

code of binary 11XXXXXX. The AF bit does not initiate

the IRQ signal when the AIE bit is set to 0. The internal

functions of the DS12R885 do not affect the AIE bit, but

is cleared to 0 on RESET.

Bit 4: Update-Ended Interrupt Enable (UIE). This bit is

a read/write bit that enables the update-end flag (UF)

bit in Register C to assert IRQ. The RESET pin going

low or the SET bit going high clears the UIE bit. UIE is

not modified by any internal DS12R885 functions, but is

cleared to 0 on RESET.

Bit 3: Square-Wave Enable (SQWE). When this bit is

set to 1, a square-wave signal at the frequency set by

the rate-selection bits RS3–RS0 is driven out on the

SQW pin. When the SQWE bit is set to 0, the SQW pin

is held low. SQWE is a read/write bit and is cleared by

RESET. SQWE is low if disabled, and is high imped-

ance when V

is below V

. SQWE is cleared to 0 on

RESET.

Bit 2: Data Mode (DM). This bit indicates whether time

and calendar information is in binary or BCD format.

The DM bit is set by the program to the appropriate for-

mat and can be read as required. This bit is not modi-

fied by internal functions or RESET. A 1 in DM signifies

binary data, while a 0 in DM specifies BCD data.

Bit 1: 24/12. The 24/12 control bit establishes the for-

mat of the hours byte. A 1 indicates the 24-hour mode

and a 0 indicates the 12-hour mode. This bit is

read/write and is not affected by internal functions or

RESET.

Bit 0: Daylight Saving Enable (DSE). This bit is a

read/write bit that enables two daylight saving adjust-

ments when DSE is set to 1. On the first Sunday in

April, the time increments from 1:59:59 AM to 3:00:00

AM. On the last Sunday in October when the time first

reaches 1:59:59 AM, it changes to 1:00:00 AM. When

DSE is enabled, the internal logic tests for the first/last

Sunday condition at midnight. If the DSE bit is not set

when the test occurs, the daylight saving function does

not operate correctly. These adjustments do not occur

when the DSE bit is 0. This bit is not affected by internal

functions or RESET.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

SET PIE AIE UIE SQWE DM 24/12 DSE

Control Register B

RTCs with Constant-Voltage Trickle Charger

DS12R885/DS12CR887/DS12R887

18 ____________________________________________________________________

Bit 7: Interrupt Request Flag (IRQF). This bit is set to

1 when any of the following are true:

PF = PIE = 1

AF = AIE = 1

UF = UIE = 1

Any time the IRQF bit is 1, the IRQ pin is driven low.

This bit can be cleared by reading Register C or with a

RESET.

Bit 6: Periodic Interrupt Flag (PF). This bit is read-

only and is set to 1 when an edge is detected on the

selected tap of the divider chain. The RS3 through RS0

bits establish the periodic rate. PF is set to 1 indepen-

dent of the state of the PIE bit. When both PF and PIE

are 1s, the IRQ signal is active and sets the IRQF bit.

This bit can be cleared by reading Register C or with a

RESET.

Bit 5: Alarm Interrupt Flag (AF). A 1 in the AF bit indi-

cates that the current time has matched the alarm time.

If the AIE bit is also 1, the IRQ pin goes low and a 1

appears in the IRQF bit. This bit can be cleared by

reading Register C or with a RESET.

Bit 4: Update-Ended Interrupt Flag (UF). This bit is

set after each update cycle. When the UIE bit is set to

1, the 1 in UF causes the IRQF bit to be a 1, which

asserts the IRQ pin. This bit can be cleared by reading

Bits 3 to 0: Unused. These bits are unused in Register

C. These bits always read 0 and cannot be written.

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

IRQF PF AF UF 0000

Control Register C

BIT 7 BIT 6 BIT 5 BIT 4 BIT 3 BIT 2 BIT 1 BIT 0

VRT0000000

Control Register D

Bit 7: Valid RAM and Time (VRT). This bit indicates

the condition of the battery connected to the V

BACKUP

pin. This bit is not writeable and should always be 1

when read. If a 0 is ever present, an exhausted internal

lithium energy source is indicated and both the con-

tents of the RTC data and RAM data are questionable.

This bit is unaffected by RESET.

Bits 6 to 0: Unused. The remaining bits of Register D

are not usable. They cannot be written and they always

RTCs with Constant-Voltage Trickle Charger

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

DS12CR887-5+

Mfr. #:

Buy DS12CR887-5+

Manufacturer:

Maxim Integrated

Description:

Real Time Clock RTC w/Constant V Trickle Charger

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DS12CR887-5+

DS12CR887-5+

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