DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
_____________________________________________________________________ 7
POWER-UP/POWER-DOWN CHARACTERISTICS
(T
A
= -40°C to +85°C) (Note 1)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Recovery at Power-Up t
RPU
20 200 ms
V
CC
Fall Time; V
PF(MAX)
to
V
PF(MIN)
t
F
300 µs
V
CC
Rise Time; V
PF(MIN)
to
V
PF(MAX)
t
R
s
CAPACITANCE
(T
A
= +25°C)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Capacitance on All Input Pins
Except X1 and X2
C
IN
(Note 9) 10 pF
Capacitance on IRQ, SQW, and
DQ Pins
C
IO
(Note 9) 10 pF
DATA RETENTION (DS12CR887)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Expected Data Retention t
DR
T
A
= +25°C 5 Years
AC TEST CONDITIONS
PARAMETER TEST CONDITIONS
Input Pulse Levels (-5) 0 to 3.0V
Input Pulse Levels (-33) 0 to 2.7V
Output Load Including Scope and Jig (-5) 50pF + 1TTL Gate
Output Load Including Scope and Jig (-33) 25pF + 1TTL Gate
Input and Output Timing Measurement Reference Levels Input/Output: V
IL
maximum and V
IH
minimum
Input-Pulse Rise and Fall Times 5ns
WARNING: Negative undershoots below -0.3V while the part is in battery-backed mode may cause loss of data.
Note 1: Limits at -40°C are guaranteed by design and not production tested.
Note 2: All voltages are referenced to ground.
Note 3: All outputs are open.
Note 4: Specified with CS = DS = R/W = RESET = V
CC
; MOT, AS, AD0–AD7 = 0; V
BACKUP
open.
Note 5: Applies to the AD0 to AD7 pins, the IRQ pin, and the SQW pin when each is in a high-impedance state.
Note 6: The MOT pin has an internal 20kΩ pulldown.
Note 7: Measured with a 32.768kHz crystal attached to X1 and X2.
Note 8: Measured with a 50pF capacitance load.
Note 9: Guaranteed by design. Not production tested.
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
8 _____________________________________________________________________
Typical Operating Characteristics
(V
CC
= +3.3V, T
A
= +25°C, unless otherwise noted.)
OSCILLATOR FREQUENCY
vs. SUPPLY VOLTAGE
DS12R885 toc04
SUPPLY (V)
FREQUENCY (Hz)
5.04.53.5 4.03.02.5
32767.92
32767.94
32767.96
32767.98
32768.00
32768.02
32768.04
32768.06
32768.08
32768.10
32767.90
2.0 5.5
I
BACKUP
vs. TEMPERATURE
(DS12R885)
DS12R885 toc03
TEMPERATURE (°C)
SUPPLY CURRENT (nA)
6550-25 -10 5 20 35
475
500
525
550
575
600
625
650
450
-40 80
V
CC
= 0V,
V
BACKUP
= 3.0V
V
BACKUP
vs. V
CC
vs. I
BACKUP
(DS12R885)
DS12R885 toc02
V
CC
(V)
V
BACKUP
(V)
5.04.54.03.53.02.52.01.5
2.2
2.4
2.6
2.8
3.0
2.0
1.0 5.5
0
μ
A
-15
μ
A
-30
μ
A
-45
μ
A
-60
μ
A
I
BACKUP
vs. V
BACKUP
(DS12R885)
DS12R885 toc01
V
BACKUP
(V)
SUPPLY CURRENT (nA)
2.82.52.3
575
600
625
550
2.0 3.0
V
CC
= 0V
DS12R885/DS12CR887/DS12R887
RTCs with Constant-Voltage Trickle Charger
_____________________________________________________________________ 9
POWER
CONTROL
AND
TRICKLE
CHARGER
V
BACKUP
OSC
BUS
INTERFACE
V
CC
X1
X2
DS12R887/
DS12CR887
ONLY
DS12R887/
DS12CR887
ONLY
RESET
CS
DS
AS
R/W
MOT
AD0–AD7
DIVIDE
BY 8
DIVIDE
BY 64
DIVIDE
BY 64
16:1 MUX
SQUARE-
WAVE
GENERATOR
REGISTERS A, B, C, D
CLOCK/CALENDAR AND
ALARM REGISTERS
USER RAM
114 BYTES
CLOCK/CALENDAR
UPDATE LOGIC
IRQ
SQW
IRQ
GENERATOR
BUFFERED CLOCK/
CALENDAR AND ALARM
REGISTERS
GND
RLCR
DS12R885
Functional Diagram
Pin Description
PIN
SO EDIP
BGA
NAME FUNCTION
1 1 C5 MOT
Motorola or Intel Bus Timing Selector. This pin selects one of two bus types. When
connected to V
CC
, Motorola bus timing is selected. When connected to GND or left
disconnected, Intel bus timing is selected. The pin has an internal pulldown resistor.
2 — — X1
3 — — X2
Connections for Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is
designed for operation with a crystal having a 12.5pF specified load capacitance (C
L
).
Pin X1 is the input to the oscillator and can optionally be connected to an external
32.768kHz oscillator. The output of the internal oscillator, pin X2, is left unconnected if
an external oscillator is connected to pin X1.
4–11 4–11
F4, D4,
F3, D3,
F2, D2,
F1, D1
AD0–
AD7
Multiplexed, Bidirectional Address/Data Bus. The addresses are presented during the first
portion of the bus cycle and latched into the DS12R885 by the falling edge of AS. Write
data is latched by the falling edge of DS (Motorola timing) or the rising edge of R/W (Intel
timing). In a read cycle, the DS12R885 outputs data during the latter portion of DS (DS and
R/W high for Motorola timing, DS low and R/W high for Intel timing). The read cycle is
terminated and the bus returns to a high-impedance state as DS transitions low in the case
of Motorola timing or as DS transitions high in the case of Intel timing.

DS12CR887-5+

Mfr. #:
Manufacturer:
Maxim Integrated
Description:
Real Time Clock RTC w/Constant V Trickle Charger
Lifecycle:
New from this manufacturer.
Delivery:
DHL FedEx Ups TNT EMS
Payment:
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