HI7188IN Datasheet HI7188IN | P13-P15

It is recommended that V

be tied to analog ground when

operating off of AV

= +5V and AV

= -5V supplies. V

also determines the headroom at the upper and lower ends

of the power supplies which is limited by the common mode

input range where the internal operational ampliﬁers remain

in the linear, high gain region of operation.

Sigma Delta Modulator

The sigma delta modulator is a fourth order modulator which

converts the differential analog signal into a series of one bit

outputs. The 1’s density of this data stream provides a digital

representation of the analog input. Figure 10 shows a

simpliﬁed block diagram of the analog modulator front end of

a Sigma-Delta A/D Converter. The input signal V

comes

into a summing junction (the PGIA in this case) where the

previous modulator output is subtracted from it. The resulting

signal is then integrated and the output of the integrator goes

into the comparator. The output of the comparator is then fed

back via a one bit DAC to the summing junction. The

feedback loop forces the average of the fed back signal to be

equal to the input signal V

Digital Section Description

A block diagram of the digital section of the HI7188 is shown

in Figure 11. This section includes an integrating ﬁlter,

averaging ﬁlters, calibration logic registers, output data RAM,

digital serial interface and a clock generator.

Integrating Filters

The integrating ﬁlter receives a stream of 1s and 0s from the

modulator at a rate of 614kHz. The 1’s density of this data

stream provides a digital representation of the analog input

signal. The integrating ﬁlter provides the low pass function

with a cutoff of 2kHz. The Integrating Filter works in concert

with the modulator and is controlled by the same clock and

reset signals. The ﬁlter integrates 201 1-bit samples from the

modulator for a valid “conversion” to be completed. At that

time the data is transferred to the Line Noise Rejection

(LNR) Filters or straight to calibration if LNR is not selected.

Line Noise Rejection

The line noise rejection section is used to eliminate a periodic

sine wave signal of either 50Hz or 60Hz line frequencies.

To understand the functionality of the HI7188 line noise

rejection (LNR), it is useful to discuss the method utilized by

a generic integrating analog to digital converter (ADC). This

ADC uses an external summing/integrating capacitor to sum

the line noise on a capacitor over one line noise cycle. The

cycle period is 16.67ms and 20ms for 60Hz and 50Hz

respectively. The ADC output is then the desired input with

the line noise summed to zero with a conversion rate equal

to the line noise frequency.

The HI7188 has the ability to do the same function as the

Integrating ADC but samples the input four times during the

line cycle (see Figure 12). For this discussion, the desired

analog input signal will be zero. The HI7188 accomplishes this

by instituting a four quadrant, four point running average

system. The microsequencer samples all eight inputs at

exactly the same point in time and for the exact amount of

time for each of the four quadrants of a single line cycle and

stores them separately. These four samples are then

summed, on a per channels basis, which results in the same

answer of the line synchronous noise as with the Integrating

ADC.

PGIA INTEGRATOR

COMPARATOR

RHI

RLO

DAC

∫

FIGURE 10. SIMPLE MODULATOR BLOCK DIAGRAM

HI7188

A one channel example:

1. Channel 1 is sampled four times as labeled S1, S2, S3,

and S4 in Figure 12. One sample for each 90 degrees

quadrant of line cycle (quarter main cycle).

2. Each sample is equally spaced (From zero, S1 = 5 degrees,

S2 = 95 degrees, S3 = 185 degrees and S4 = 275 degrees).

3. Each sample is of the same duration of time.

4. Samples S1 and S3 (180 degrees later) will have the

equal magnitudes of line noise but have opposite signs.

5. Samples S2 and S4 (180 degrees later) will have the

equal magnitudes but opposite signs.

6. The HI7188 sums the samples S1, S3, S2 and S4 which

results in averaging the line noise signal to zero.

7. These four samples are placed, real time, in the 4x8 array

of registers used for LNR. The next quadrant sampled (S5)

replaces S1 in the running average. The new sample

replaced S1 at the same point on the line cycle, 5 degrees

but 360 degrees later. The line noise summation is still

zero. Now for every quarter main cycle thereafter, the LNR

will be updated and line noise free output will be available.

Calibration

Calibration is the process of adjusting the conversion data

based on known system offset and gain errors. For a

complete system calibration to occur, the on-chip

microcontroller must perform a three point calibration which

involves recording conversion results for three different input

conditions - “zero-scale,” “positive full-scale,” and “negative

full-scale”. With these readings, the HI7188 can null any

system offset errors and calculate the positive and negative

gain slope factors for the transfer function of the system. It is

CONVERSION CONTROL

SERIAL

INTERFACE

CLOCK

GENERATOR

OSC1 OSC2

CAEOS MODE CSRST RSTIOSDIOSDOSCLK

CONTROL

CALIBRATION

REGISTERS

AND CONTROL

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

INTEGRATING

FILTER

FROM

ANALOG

SECTION

LOGICAL SEQUENCER

CCR REGISTERS

LOGICAL

CHANNEL

ADDRESS

FIGURE 11. DIGITAL BLOCK DIAGRAM

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

CH1

CH2

CH3

CH4

CH5

CH6

CH7

CH8

RAM0 RAM1

LOGICAL

CHANNELS

BYPASS

LNR

LINE NOISE FILTER

TIME

LINE NOISE

FIGURE 12. LINE NOISE CYCLE INCLUDING PATENTED TIME

SPACED INPUT SAMPLING

HI7188

imperative that the zero-scale calibration be performed

before either of the gain calibrations. The order of the gain

calibrations is not important. Non-calibrated data can be

obtained from the device by writing 000000 (h) to the Offset

Calibration Register, 800000 (h) to the Positive Full Scale

Calibration Register, and 800000 (h) to the Negative Full

Scale Calibration Register. This sets the offset of the part to

0 and both the positive and negative gain slope factors to 1.

A calibration routine should be initiated whenever there is a

change in the ambient operating temperature or supply

voltage. It should also be initiated if there is a change in the

gain, bipolar, or unipolar input range.

The user may choose to ignore data during calibration or

check whether any ACTIVE channel is in calibration. Bit 12,

the SE bit, of the Control Register offers capability to

suppress the

EOS interrupt during calibration. If the SE bit is

high the

EOS interrupt will be suppressed if any active

logical channel is in the calibration mode. If the SE bit is high

and no active logical channels are in the calibration mode

the

EOS interrupt will function normally. If low, the suppress

EOS function is disabled. To check whether any logical

channel is in calibration the user can monitor the Calibration

Active (CA) output pin. The CA output pin is high when at

least one of the active logical channels are in calibration. If a

non active logical channel is in calibration the CA will not be

high. The user can monitor the CA pin to determine when all

active logical channels are calibrated.

NOTE: When the user accesses the calibration RAMs, via the Serial

Interface, the conversion process stops, resetting the modulator,

integrating ﬁlter and clearing the EOS interrupt. When the calibration

RAM I/O operation is completed the device automatically restarts

beginning on logical channel 1. The contents of the CR and CCR are

not affected by this I/O.

Calibration Time

The calibration time varies depending several factors

including LNR (50Hz/60Hz) being enabled or disabled, and 2

point calibration. Table 3 contains a summary of the

conversion time depending on these factors. Since line noise

rejection is a major factor this discussion is divided

accordingly.

Line Noise Rejection On

When line noise rejection is enabled, it takes 4 conversion

scan periods to ﬁll the averaging ﬁlters used for attenuating

the periodic line noise. A conversion scan involves

converting all 8 logical channels at a rate dependent on

whether LNR is set to 50Hz or 60Hz. The scan period is 5ms

(1/200Hz) and 4.167ms (1/240Hz) respectively. The number

of active channels is not applicable in this calculation since

the microsequencer converts on ALL logical channels to

maintain LNR timing regardless of the number of user

deﬁned active channels.

Line Noise Rejection Off

Operation of the device is altered slightly when LNR is

disabled. Since the microsequencer is not synchronizing for

any line noise, the conversion rate increases to 260.3

conversions second/channel (10% increase). With LNR

disabled, a conversion scan involves converting only the

ACTIVE logical channels. When ACTIVELY converting on

less than 8 channels, this is the major speed advantage over

LNR enabled which sets conversion scan period based on

ALL eight logical channels. Refer to Table 3.

System Offset Calibration

The system offset calibration mode is a process that allows

the user to lump offset errors of external circuitry and the

internal errors of the HI7188 together and null them out. This

mode will convert the external differential signal applied to

the V

inputs and then store that value in the offset

calibration RAM for that physical channel. To invoke the

system offset calibration the user applies the “zero scale”

voltage to the physical channel requiring calibration, then

writes the related CCR byte indicating offset calibration is

required. The next time this logical channel is converted, the

microsequencer performs calibration and updates the

related offset RAM. Next the internal microsequencer places

that logical channel back into the conversion mode and

updates the CCR byte.

System Positive Full Scale Calibration

The system positive full scale calibration mode is a process

that allows the user to lump positive gain errors of external

circuitry and the internal gain errors of the HI7188 together to

calculate the positive transfer function of the system. This

mode will convert the external differential signal applied to the

inputs and then store that value in the system positive full

Scale calibration RAM for that physical channel. To invoke the

system positive full scale calibration the user applies the

“positive full scale” voltage to the physical channel requiring

calibration, then writes the related CCR byte indicating

positive full scale calibration is required. The next time this

logical channel is converted, the microsequencer performs

calibration and updates the related system positive full scale

calibration RAM. Next the internal microsequencer places that

logical channel back into the conversion mode and updates

the CCR byte.

TABLE 3. CALIBRATION TIME

LNR

FREQ

(Hz)

ACTIVE

CHANS

CAL

PNTS

EACH

CAL

POINT

(ms)

TOTAL

CAL

(ms)

On 50 n/a 2 20 40

On 50 n/a 3 20 60

On 60 n/a 2 16.7 33.3

On 60 n/a 3 16.7 50.0

Off n/a N 2.5

N (0.4803) 2N (0.4803)

Off n/a N 3 N (0.4803) 3N (0.4803)

NOTE: N is the number of active channels. Total Cal column

assumes zero switching time between calibration points.

HI7188

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24

HI7188IN

Mfr. #:

Buy HI7188IN

Manufacturer:

Renesas / Intersil

Description:

IC ADC 16BIT SIGMA-DELTA 44MQFP

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

Products related to this Datasheet

HI7188IN