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HI7188IN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
7
TIMING CHARACTERISTICS
SCLK Minimum Cycle Time, t
SCLK
(Notes 2, 7) 200 - - ns
SCLK Minimum Pulse Width, t
SCLKPW
(Notes 2, 7) 60 - - ns
CS to SCLK Precharge Time, t
PRE
(Notes 2, 7) 50 - - ns
Data Setup to SCLK Rising Edge (Write),
t
DSU
(Notes 2, 7) 50 - - ns
Data Hold from SCLK Rising Edge
(Write), t
DHLD
(Notes 2, 7) 0 - - ns
Data Read Access from Instruction Byte
Write, t
ACC
(Notes 2, 7) - - 40 ns
Read Bit Valid from SCLK Falling Edge,
t
DV
(Notes 2, 7) - - 40 ns
Last Data Transfer to Data Ready
Inactive, t
DRDY
(Notes 2, 7) - 50 - ns
RESET Low Pulse Width t
RESET
(Notes 2, 7) 100 - - ns
RSTI/O Low Pulse Width t
RSTI/O
(Notes 2, 7) 100 - - ns
MUX High Pulse Width t
MUX
(Notes 2, 7) 14 - - µs
CADDR Valid to MUX High (Notes 2, 7) - - 75 ns
Oscillator Clock Frequency (Notes 2, 7) - 3.6864 - MHz
Output Rise/Fall Time (Notes 2, 7) - - 30 ns
Input Rise/Fall Time (Notes 2, 7) - - 1 µs
POWER SUPPLY CHARACTERISTICS
IAV
DD
AV
DD
= +5V, OSC
1
= 3.6864MHz (Note 3) - 1.8 3.0 mA
IAV
SS
AV
SS
= -5V, OSC
1
= 3.6864MHz (Note 3) - 1.8 3.0 mA
IDV
DD
DV
DD
= +5V, SCLK = 4MHz - 2.0 4.0 mA
Power Dissipation, Active PD
A
AV
DD
= +5V, AV
SS
= -5V, SLP = ‘0’
(Notes 3, 9)
-2850mW
Power Dissipation, Sleep PD
S
AV
DD
= +5V, AV
SS
= -5V, SLP = ‘1’
(Notes 3, 9)
-5-mW
PSRR (∆ V
supply
= 0.25V) PSRR = 20log (∆V
supply
/ ∆V
OS
) (Note 3) - 75 - dB
NOTES:
2. Parameter guaranteed by design or characterization, not production tested.
3. DC PSRR is measured on all supplies individually and applies to both Bipolar and Unipolar Input Ranges.
4. These errors can be removed by re-calibrating at the desired operating temperature.
5. Applies after system calibration.
6. Fully differential input signal source is used.
7. See Load Test Circuit, Figure 1, R
1
= 10kΩ, C
L
= 50pF (Includes Stray and Jig Capacitance).
8. For Line Noise Rejection, 3.6864MHz is required to develop internal clocks to reject 50/60Hz.
9. SLP is the sleep mode enable bit defined in bit 3 of the Control Register (CR <3>).
Electrical Specifications AV
DD
= +5V, AV
SS
= -5V, DV
DD
= +5V, V
RHI
= +2.5V, V
RLO
= AGND, V
CM
= AGND, PGIA Gain = 1,
OSC
IN
= 3.6864MHz, Bipolar Input Range Selected (Continued)
PARAMETER TEST CONDITION
-40
o
C TO 85
o
C
UNITSMIN TYP MAX
HI7188
8
Test Circuits
FIGURE 1. LOAD TEST CIRCUIT
FIGURE 2. HUMAN BODY AND MACHINE MODEL ESD TEST
CIRCUIT
FIGURE 3. CHARGE DEVICE MODEL ESD TEST CIRCUIT
Waveforms
FIGURE 4. DATA WRITE TO HI7188
V
1
R
1
C
L
(INCLUDES STRAY
DUT
CAPACITANCE)
DUT
HUMAN BODY
C
ESD
= 100pF
MACHINE MODEL
C
ESD
= 200pF
R
1
C
ESD
R
1
= 10MΩ
R
1
= 10MΩ
R
2
R
2
= 1.5kΩ
R
2
= 0Ω
±
V
CHARGED DEVICE MODEL
R
1
R
1
= 1GΩ
R
2
R
2
= 1Ω
±
DUT
DIELECTRIC
V
1ST BIT 2ND BIT
CS
SCLK
SDIO
t
EN
t
PRE
t
SCLK
t
SCLKPW
t
DHLD
t
DSU
t
SCLKPW
HI7188
9
Definitions
Integral Non-Linearity (INL) - This is the maximum
deviation of any digital code from a straight line passing
through the endpoints of the transfer function. The endpoints
of the transfer function are zero scale (a point 0.5 LSB below
the first code transition 000...000 and 000...001) and full scale
(a point 0.5 LSB above the last code transition 111...110 to
111...111).
Differential Non-Linearity (DNL) - This is the deviation
from the actual difference between midpoints and the ideal
difference between midpoints (1 LSB) for adjacent codes. If
this difference is equal to or more negative than 1 LSB, a
code will be missed.
Offset Error (V
OS
)-The offset error is the deviation of the first
code transition from the ideal input voltage (V
IN
- 0.5 LSB).
Full Scale Error (FSE) - The full scale error is the deviation
of the last code transition from the ideal input full-scale
voltage (V
IN
- + V
REF
/Gain - 1.5 LSB).
Input Span - The input span defines the minimum and
maximum input voltages the device can handle while still
calibrating properly for gain.
End of Scan (EOS) - The end of scan is a signal used to
indicate all active logical channels have been converted and
data is available to be read.
Line Noise Rejection - Line noise rejection is the ability to
attenuate (reject) signals at the frequency of power lines
typically 50Hz or 60Hz.
Physical/Logical Channel - A physical channel pertains to
channels which are directly connected to the device package
pins identified in the pinout. Logical channels are predefined
in the Channel Configuration Registers (CCR) with a physical
channels reference (address) being made by the user. Refer
to the Channel Configuration Registers section for examples.
FIGURE 5. DATA READ FROM HI7188
FIGURE 6. DATA READ FROM HI7188
Waveforms (Continued)
CS
SCLK
SDIO
SDO
t
ACC
1ST BIT 2ND BIT
t
DV
SCLK
CS
EOS
SDIO
t
EOS
87651
HI7188
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

HI7188IN

Mfr. #:
Buy HI7188IN
Manufacturer:
Renesas / Intersil
Description:
IC ADC 16BIT SIGMA-DELTA 44MQFP
Lifecycle:
New from this manufacturer.
Delivery:
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