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HI7188IN

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24
19
Detailed Register Descriptions
Instruction Register
The instruction register is an 8 bit register which is used
during a communications cycle for setting up read/write
operations. Below are the bit assignments.
R/W - Bit 7 of the Instruction Byte determines whether phase
2 of the communication cycle will be a read or write
operation. If
R/W is logic 1, a write transfer will occur in
phase 2 of the communication cycle. If
R/W is logic 0, a read
transfer will occur in phase 2 of the communication cycle.
NB1, NB0 - Bits 6 and 5 of the Instruction Byte determine the
number of bytes that will be transferred during phase 2 of a
communication cycle, if a register is selected for I/O access. If a
RAM is selected for IO access, these bits are don’t care. Any
number of bytes from 1 to 4 is allowed. See Tables 6 and 7.
RB - Bit 4 is used to determine the byte order when accessing
a RAM address. When accessing a RAM address, if RB = 1,
the data format is most significant byte first to least significant
byte. When accessing a RAM address, if RB = 0, the data
format is least significant byte first to most significant byte.
When accessing a register address, this bit is a don’t care.
A3, A2, A1, A0 - Bits 3 and 2 (A3 and A2) of the Instruction
Byte determine which of the three internal registers will be
accessed or if both bits are set (11b), that a RAM access is
active. For register addresses, bits 1 and 0 (A1 and A0)
determine which byte of that register will be accessed first.
For RAM access (A3 = 1, A2 = 1), bits 1 and 0 (A1 and A0)
determine which RAM is the source or destination.
INSTRUCTION REGISTER (BYTE)
MSB654321LSB
R/W NB1 NB0 RB A3 A2 A1 A0
TABLE 6. MULTIPLE BYTE ACCESS BITS
NB1, NB0 IR [6:5] DESCRIPTION
00 Transfer 1 Byte
01 Transfer 2 Bytes
10 Transfer 3 Bytes
11 Transfer 4 Bytes
TABLE 7. INTERNAL REGISTER ADDRESS
R/W
IR [7]
NB1,
NB0
IR [6:5]
A3, A2,
A1, A0
IR [3:0] DESCRIPTION
0/1 00 0000 CR, start byte 0, 1 byte transfer
0/1 01 0000 CR, start byte 0, 2 byte transfer
0/1 00 0001 CR, start byte 1, 1 byte transfer
0/1 01 0001 CR, start byte 1, 2 byte transfer
0/1 00 0100 CCR #1, start byte 0, 1 byte transfer
0/1 00 0101 CCR #1, start byte 1, 1 byte transfer
0/1 00 0110 CCR #1, start byte 2, 1 byte transfer
0/1 00 0111 CCR #1, start byte 3, 1 byte transfer
0/1 01 0100 CCR #1, start byte 0, 2 byte transfer
0/1 01 0101 CCR #1, start byte 1, 2 byte transfer
0/1 01 0110 CCR #1, start byte 2, 2 byte transfer
0/1 01 0111 CCR #1, start byte 3, 2 byte transfer
0/1 10 0100 CCR #1, start byte 0, 3 byte transfer
0/1 10 0101 CCR #1, start byte 1, 3 byte transfer
0/1 10 0110 CCR #1, start byte 2, 3 byte transfer
0/1 10 0111 CCR #1, start byte 3, 3 byte transfer
0/1 11 0100 CCR #1, start byte 0, 4 byte transfer
0/1 11 0101 CCR #1, start byte 1, 4 byte transfer
0/1 11 0110 CCR #1, start byte 2, 4 byte transfer
0/1 11 0111 CCR #1, start byte 3, 4 byte transfer
0/1 00 1000 CCR #2, start byte 0, 1 byte transfer
0/1 00 1001 CCR #2, start byte 1, 1 byte transfer
0/1 00 1010 CCR #2, start byte 2, 1 byte transfer
0/1 00 1011 CCR #2, start byte 3, 1 byte transfer
0/1 01 1000 CCR #2, start byte 0, 2 byte transfer
0/1 01 1001 CCR #2, start byte 1, 2 byte transfer
0/1 01 1010 CCR #2, start byte 2, 2 byte transfer
0/1 01 1011 CCR #2, start byte 3, 2 byte transfer
0/1 10 1000 CCR #2, start byte 0, 3 byte transfer
0/1 10 1001 CCR #2, start byte 1, 3 byte transfer
0/1 10 1010 CCR #2, start byte 2, 3 byte transfer
0/1 10 1011 CCR #2, start byte 3, 3 byte transfer
0/1 11 1000 CCR #2, start byte 0, 4 byte transfer
0/1 11 1001 CCR #2, start byte 1, 4 byte transfer
0/1 11 1010 CCR #2, start byte 2, 4 byte transfer
0/1 11 1011 CCR #2, start byte 3, 4 byte transfer
0 xx 1100 Data RAM burst transfer, least
significant byte first, READ ONLY
0 xx 1100 Data RAM burst transfer, most
significant byte first, READ ONLY
0/1 xx 1101 Offset RAM burst transfer, least
significant byte first.
0/1 xx 1101 Offset RAM burst transfer, most
significant byte first.
0/1 xx 1110 Positive full scale RAM burst transfer,
least significant byte first.
0/1 xx 1110 Positive full scale RAM burst transfer,
most significant byte first.
0/1 xx 1111 Negative full scale RAM burst transfer,
least significant byte first.
0/1 xx 1111 Negative full scale RAM burst transfer,
most significant byte first.
TABLE 7. INTERNAL REGISTER ADDRESS (Continued)
R/W
IR [7]
NB1,
NB0
IR [6:5]
A3, A2,
A1, A0
IR [3:0] DESCRIPTION
HI7188
20
Control Register
The Control Register (CR) is 16 bits wide and contains
information that determines operating mode and the
system/chip level configuration. This configuration applies to
all logical channels and cannot be modified at the channel
level. Following are the bit assignments:
T3, T2, T1 - Bits 15, 14 and 13 are reserved and MUST
always be logic zero for normal operation. These bits are low
after
RESET is applied.
CHOP. Bit 12 is the active low chop bit used to determine
whether the chopper stabilized amplifier is used or
bypassed. This bit is low (chop on) after
RESET is applied.
SE. Bit 11 is the active high suppress EOS bit. If high, the
EOS interrupt will not go active when any logical channel is
in calibration mode. If this bit is high and no logical channels
are in the calibration mode, or this bit is low,
EOS
functionality is as previously described. This bit allows the
user to suppress false
EOS interrupts during calibration.
Only logical channels that are actively being converted are
considered. That is, if only two logical channels are being
converted but the CCR byte for a non active logical channel
is in a calibration mode, the
EOS functionality is active. This
bit is low (suppress
EOS off) after RESET is applied.
LNR. Bit 10 is the active high line noise rejection (LNR) bit. If
high LNR is selected. This bit is low (LNR off) after
RESET is
applied.
FS. Bit 9 is the 50Hz/60Hz frequency select bit. If bit 9 is
high, the clock generation logic synchronizes conversions for
proper rejection of 50Hz line noise. If bit 9 is low, the clock
generation logic synchronizes conversions for proper
rejection of 60Hz line noise. This bit is low (60Hz LNR) after
RESET is applied.
TC. Bit 8 is the active high two’s complement bit used to
select between 2’s complementary and offset binary data
coding for bipolar mode. In bipolar mode, a high selects
two’s complement; when low data is offset binary. Note that
in unipolar mode the binary data coding is not affected by
the TC bit. This bit is low (offset binary data) after RESET is
applied.
N2, N1, N0. Bits 7, 6 and 5 are the bits that specify the number
of active logical channels to be converted. See Table 8. These
bits are low (one active channel) after RESET is applied.
TP - Bit 4 is the active high two point calibration bit. When
high, the positive gain slope factor is used for both positive
and negative voltages. This bit is low (normal three point cal)
after
RESET is applied.
SLP - Bit 3 is the active high sleep mode bit used to put the
device in a low power/standby mode. When high, conversion
stops and the conversion pointer is reset to logical channel
1. The four line noise rejection filters are cleared and
EOS is
deactivated. The serial interface, calibration/data RAMs, CR
and CCR are not affected.
To return from sleep mode the user changes this bit from
high to low. This restarts the conversion process beginning
with logical channel 1. If line noise rejection is enabled, it
takes four complete scans (all active channels) to refill the
four line noise rejection filters before an
EOS interrupt. If line
noise rejection not enabled, it takes 1 complete scan before
an
EOS interrupt.
This bit is low (sleep mode off) after RESET is applied.
BD. Bit 2 is the byte direction bit used to determine either
ascending or descending order access for multi-byte
transfers. When high, ascending order is enabled. When low,
descending order is enabled. This bit is low (descending
order) after
RESET is applied.
MSB. Bit 1 bit direction bit used to select whether a serial
data transfer is MSB or LSB first. When low, MSB first mode
is enabled while high selects LSB first. This bit is low (MSB
first) after
RESET is applied.
SDL. Bit 0 selects a two-wire or three-wire transfer protocol of
the serial interface. When low, two-wire data transfers are done
using the SDIO pin. Both data in and out of the part is uses the
by-directional SDIO pin. When high, three-wire data transfers
are done using the SDIO and SDO pins. Data into the part uses
the SDIO pin while data out uses the SDO pin. This bit is low
(two-wire, SDIO exclusively) after
RESET is applied.
Channel Configuration Registers
The HI7188 Channel Configuration Registers (CCR) comprise
a 64-bit memory element that defines the logical channel
conversion order as well as each logical channel specific data
such as physical channel address, mode, gain, and
CONTROL REGISTER BYTE 1
MSB 14 13 12 11 10 9 LSB
T3 T2 T1 CHOP SE LNR FS TC
CONTROL REGISTER BYTE 0
MSB654321LSB
N2 N1 N0 TP SLP BD MSB SDL
TABLE 8. NUMBER OF CONVERSION CHANNELS
N2, N1, N0 CR [7:5] NUMBER OF CHANNELS TO CONVERT
000 1
001 2
010 3
011 4
100 5
101 6
110 7
111 8
HI7188
21
bipolar/unipolar operation. The 64 bits are divided into two 32
bit register blocks referred to as CCR#2 and CCR#1. Each
register contains four bytes pertaining to four logical channels.
The register may be accessed 1, 2, 3 or 4 bytes at a time.
Please refer to Table 10 to determine physical address
assignments within the CCR and Table 9 for logical channel
assignment. The physical channel conversion order is defined
based on it’s location in the CCR blocks. For example, if the
CCR #2 <31:24> is set with the CCR <2:0> = 100, then
physical channel 5 will be converted first. The CCR is byte wide
accessible via the Serial Interface allowing the user to change
the individual logical channel configuration on the fly. Following
are the bit assignments.
CH2, CH1, CH0 - Bits 7, 6, 5 of the channel configuration byte
determine which physical inputs are used as shown in Table 10.
B/
U - Bit 4 of the channel configuration byte determine
bipolar or unipolar mode. If Logic 1, bipolar mode is selected
while logic 0 selects unipolar mode.
MD1, MD0 - Bit 3 and 2 of the channel configuration byte are
the channel Mode bits. This defines the mode of operation
for that logical channel, please see Table 11. All calibration
modes automatically return to conversion mode after
calibration is complete.
G1, G0 - Bit 1 and 0 defines the PGIA gain of 1, 2, 4 or 8.
Please refer to Table 12.
Serial Interface Pin Description
The serial I/O port is a bidirectional port which is used to
read and write the internal registers. The port contains two
data lines, a synchronous clock, and two status flags.
Figure 14 shows a diagram of the serial interface lines.
SDO - Serial Data Out. Data is read from this line using those
protocols with separate lines for transmitting and receiving
data. An example of such a standard is the Motorola Serial
Peripheral Interface (SPI) using the 68HC05 and 68HC11
family of microcontrollers, or other similar processors. In the
case of using bidirectional data transfer on SDIO, the SDO
does not output data and is set in a high impedance state.
SDIO. Serial Data In or Out. Data is always written to the
device on this line. However, this line can be used as a
bidirectional data line. This is done by properly setting up the
Control Register. Bidirectional data transfer on this line can
be used with Intel standard serial interfaces (SSR, Mode 0)
in MCS51 and MCS96 family of microcontrollers, or other
similar processors.
SCLK. Serial Clock. The serial clock pin is used to
synchronize data to and from the HI7188 and to run the port
state machines. In Synchronous External Clock Mode, SCLK
is configured as an input, is supplied by the user, and can run
up to a 5MHz rate. In Synchronous Self Clocking Mode, SCLK
is configured as an output and runs at OSC
1
/8 = 460.8kHz.
TABLE 9. CHANNEL CONFIGURATION REGISTER
BLOCK
BIT
LOCATION DESCRIPTION
CCR #2 <31:24> 1st Logical Channel
CCR #2 <23:16> 2nd Logical Channel
CCR #2 <15:8> 3rd Logical Channel
CCR #2 <7:0> 4th Logical Channel
CCR #1 <31:24> 5th Logical Channel
CCR #1 <23:16> 6th Logical Channel
CCR #1 <15:8> 7th Logical Channel
CCR #1 <7:0> 8th Logical Channel
CHANNEL CONFIGURATION REGISTER (BYTE)
MSB654321LSB
CH2 CH1 CH0 B/
U MD1 MD0 G1 G0
TABLE 10. ACTIVE CHANNEL DECODE
CH2, CH1, CH0 CCR [2:0] PHYSICAL INPUT PINS
000 V
INH1
, V
INL1
001 V
INH2
, V
INL2
010 V
INH3
, V
INL3
011 V
INH4
, V
INL4
100 V
INH5
, V
INL5
101 V
INH6
, V
INL6
110 V
INH7
, V
INL7
111 V
INH8
, V
INL8
TABLE 11. HI7188 OPERATIONAL MODES
MD1 MD0 OPERATIONAL MODE
0 0 Conversion
0 1 System Offset Calibration
1 0 System Positive Full Scale Calibration
1 1 System Negative Full Scale Calibration
TABLE 12. CHANNEL GAIN
G1, G0 CCR [1:0] PGIA CHANNEL GAIN
00 1
01 2
10 4
11 8
SDO
SDIO
SCLK
CS
EOS
CHIP SELECT
BIDIRECTIONAL
DATA
DATA OUT
PORT CLOCK
CA
CALIBRATION
MODE
CLOCK MODE
ACTIVE
END OF SCAN
HI7188
RSTI/O
RESET I/O
FIGURE 14. HI7188 SERIAL INTERFACE
HI7188
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24

HI7188IN

Mfr. #:
Buy HI7188IN
Manufacturer:
Renesas / Intersil
Description:
IC ADC 16BIT SIGMA-DELTA 44MQFP
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