ISPLSI 2064VE-280LB100

10
Specifications ispLSI 2064VE
Power Consumption
Power consumption in the ispLSI 2064VE device de-
pends on two primary factors: the speed at which the
device is operating and the number of Product Terms
used. Figure 3 shows the relationship between power
and operating speed.
Figure 3. Typical Device Power Consumption vs fmax
0127/2064VE
I
CC
can be estimated for the ispLSI 2064VE using the following equation:
I
CC
(mA) = 8 + (# of PTs * 0.67) + (# of Nets * Fmax * 0.0045)
Where:
# of PTs = Number of Product Terms used in design
# of nets = Number of Signals used in device
Max freq = Highest Clock Frequency to the device (in MHz)
The I
CC
estimate is based on typical conditions (V
CC
= 3.3V, room temperature) and an assumption of two GLB
loads on average exists. These values are for estimates only. Since the value of I
CC
is sensitive to operating
conditions and the program in the device, the actual I
CC
should be verified.
Notes: Configuration of four 16-bit counters
Typical current at 3.3V, 25° C
100
140
050100 150 200 250 300
fmax (MHz)
ispLSI 2064VE
160
180
120
80
I
CC (mA)
11
Specifications ispLSI 2064VE
32-I/O Signal Descriptions
GOE 0/IN 3 This pin performs one of two functions. It can be programmed to function as a Global Output Enable
pin or a Dedicated Input pin.
GOE 1/Y0 This pin performs one of two functions. (1) It can be programmed to function as a GLobal Output Enable
or a Dedicated Clock input. (2) This clock input is connected to one of the clock inputs of all GLBs on
the device.
RESET/Y1 This pin performs two functions: (1) Active Low (0) Reset pin which resets all of the registers in the
device. (2) When active low (0), it functions as a dedicated clock input.
BSCAN Input – Dedicated in-system programming Boundary Scan Enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. (2) When BSCAN is high, it functions as a dedicated input
pin.
TMS/IN 2 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TDO/IN 1 Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
TCK/Y2 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated clock input.
GND Ground (GND)
VCC Vcc
NC
1
No Connect
I/O Input/Output pins – These are the general purpose I/O pins used by the logic array.
64-I/O Signal Descriptions
RESET Active Low (0) Reset pin resets all the registers in the device.
GOE 0, GOE1 Global Output Enable input pins.
Y0, Y1, Y2 Dedicated Clock Input – These clock inputs are connected to one of the clock inputs of all the GLBs in
the device.
BSCAN Input – Dedicated in-system programming Boundary Scan enable input pin. This pin is brought low to
enable the programming mode. The TMS, TDI, TDO and TCK controls become active.
TDI/IN 0 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a serial data input
pin to load programming data into the device. When BSCAN is high, it functions as a dedicated input pin.
TCK/IN 3 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a clock pin for the
Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TMS/IN 1 Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as a mode control pin
for the Boundary Scan state machine. (2) When BSCAN is high, it functions as a dedicated input pin.
TDO/IN 2 Output/Input – This pin performs two functions. (1) When BSCAN is logic low, it functions as an output
pin to read serial shift register data. (2) When BSCAN is high, it functions as a dedicated input pin.
GND Ground (GND)
VCC Vcc
NC
1
No Connect
I/O Input/Output Pins – These are the general purpose I/O pins used by the logic array.
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
Signal Name Description
1. NC pins are not to be connected to any active signals, VCC or GND.
12
Specifications ispLSI 2064VE
64-I/O Signal Locations
32-I/O Signal Locations
langiSAGBacllaB-001PFQTniP-001
TESER
2D11
1EOG,0EOG1E,9F31,26
2Y,1Y,0Y8F,6F,3E06,56,01
NACSB
5E51
0NI/IDT2F61
3NI/KCT01G95
1NI/SMT5J73
2NI/ODT6B78
DNG6K,9G,1F,7B68,16,93,41
CCV4J,01F,2E,5A98,36,63,21
CN
1
,4C,3C,8A,6A
,7E,8D,6D,1D
,4F,01E,9E
,8H,7H,5G,3G
5K,3K
,52,12,9,4
,05,44,83,13
,17,66,46,45
,49,88,18,57
001
,slangisevitcaynaotdetcennocebottonerasnipCN.1
.DNGroCCV
langiSPFQTniP-44CCLPniP-44
3NI/0EOG042
0Y/1EOG5 11
TESER 1Y/
9253
NACSB
731
0NI/IDT8 41
2NI/SMT0363
1NI/ODT8142
2Y/KCT7233
DNG93,7132,1
CCV82,643,21
CN
1
——
,slangisevitcaynaotdetcennocebottonerasnipCN.1
.DNGroCCV
I/O Locations
I/O 0 G1 17 9 15
I/O 1 F3 18 10 16
I/O 2 E4 19 11 17
I/O 3 H1 20 12 18
I/O 4 G2 22 13 19
I/O 5 J1 23 14 20
I/O 6 H2 24 15 21
I/O 7 K1 26 16 22
I/O 8 J2 27 19 25
I/O 9 K2 28 20 26
I/O 10 H3 29 21 27
I/O 11 J3 30 22 28
I/O 12 G4 32 23 29
I/O 13 H4 33 24 30
I/O 14 K4 34 25 31
I/O 15 H5 35 26 32
I/O 16 F5 40 31 37
I/O 17 J6 41 32 38
I/O 18 K7 42 33 39
I/O 19 H6 43 34 40
I/O 20 K8 45 35 41
I/O 21 G6 46 36 42
I/O 22 J7 47 37 43
I/O 23 K9 48 38 44
I/O 24 J8 49 41 3
I/O 25 K10 51 42 4
I/O 26 J9 52 43 5
I/O 27 J10 53 44 6
I/O 28 H9 55 1 7
I/O 29 H10 56 2 8
I/O 30 G7 57 3 9
I/O 31 G8 58 4 10
I/O 32 D10 67
I/O 33 E8 68
I/O 34 F7 69
I/O 35 C10 70
I/O 36 D9 72
I/O 37 B10 73
I/O 38 C9 74
I/O 39 A10 76
I/O 40 B9 77
I/O 41 A9 78
I/O 42 C8 79
I/O 43 B8 80
I/O 44 D7 82
I/O 45 C7 83
I/O 46 A7 84
I/O 47 C6 85
I/O 48 E6 90
I/O 49 B5 91
I/O 50 A4 92
I/O 51 C5 93
I/O 52 A3 95
I/O 53 D5 96
I/O 54 B4 97
I/O 55 A2 98
I/O 56 B3 99
I/O 57 A1 1
I/O 58 B2 2
I/O 59 B1 3
I/O 60 C2 5
I/O 61 C1 6
I/O 62 D4 7
I/O 63 D3 8
100 100 44 44
Signal caBGA TQFP TQFP PLCC

ISPLSI 2064VE-280LB100

Mfr. #:
Manufacturer:
Lattice
Description:
CPLD ispLSI® 2000VE Family 2K Gates 64 Macro Cells 280MHz 3.3V 100-Pin CABGA
Lifecycle:
New from this manufacturer.
Delivery:
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Payment:
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