7
Specifications ispLSI 2064VE
Internal Timing Parameters
1
Over Recommended Operating Conditions
t
io
1. Internal Timing Parameters are not tested and are for reference only.
2. Refer to Timing Model in this data sheet for further details.
3. The XOR adjacent path can only be used by hard macros.
Table 2-0036A/2064VE v.0.0
Inputs
UNITS
-280 -200
MIN. MIN.MAX. MAX.
DESCRIPTION#
2
PARAMETER
20 Input Buffer Delay ns
t
din
21 Dedicated Input Delay ns
t
grp
22 GRP Delay
ns
GLB
t
1ptxor
25 1 Product Term/XOR Path Delay ns
t
20ptxor
26 20 Product Term/XOR Path Delay ns
t
xoradj
27 XOR Adjacent Path Delay ns
t
gbp
28 GLB Register Bypass Delay ns
t
gsu
29 GLB Register Setup Time before Clock ns
t
gh
30 GLB Register Hold Time after Clock ns
t
gco
31 GLB Register Clock to Output Delay ns
3
t
gro
32 GLB Register Reset to Output Delay ns
t
ptre
33 GLB Product Term Reset to Register Delay ns
t
ptoe
34 GLB Product Term Output Enable to I/O Cell Delay ns
t
ptck
35 GLB Product Term Clock Delay ns
ORP
t
ob
38 Output Buffer Delay ns
t
sl
39 Output Slew Limited Delay Adder ns
GRP
t
4ptbpc
23 4 Product Term Bypass Path Delay (Combinatorial) ns
t
4ptbpr
24 4 Product Term Bypass Path Delay (Registered) ns
t
orp
36 ORP Delay ns
t
orpbp
37 ORP Bypass Delay
ns
Outputs
t
oen
40 I/O Cell OE to Output Enabled ns
t
odis
41 I/O Cell OE to Output Disabled ns
t
goe
42 Global Output Enable ns
t
gy0
43 Clock Delay, Y0 to Global GLB Clock Line (Ref. clock) ns
t
gy1/2
44 Clock Delay, Y1 or Y2 to Global GLB Clock Line ns
Clocks
t
gr
45 Global Reset to GLB
0.4
0.8
0.4
2.3
2.3
2.3
0.0
–
–
0.2
0.4
4.1
2.9
2.9
1.2
1.8
1.1
1.6
1.2
0.4
2.3
2.3
1.2
0.7
0.9
3.5
–
–
–
–
–
–
–
0.6
1.7
–
–
–
–
0.8
–
–
–
–
–
–
–
–
–
0.7
0.9
–
0.5
1.1
0.6
2.9
2.9
2.9
0.0
–
–
0.3
0.4
4.3
3.9
4.0
1.5
2.0
1.4
1.9
1.5
0.5
3.0
3.0
2.0
1.2
1.4
3.6
–
–
–
–
–
–
–
1.2
1.8
–
–
–
–
1.0
–
–
–
–
–
–
–
–
–
1.2
1.4
–ns
Global Reset
