AD9764ARU Datasheet AD9764ARUZ, AD9764ARZ, AD9764AR | P10-P12

REV. C

AD9764

–9–

FUNCTIONAL DESCRIPTION

Figure 21 shows a simplified block diagram of the AD9764. The

AD9764 consists of a large PMOS current source array that is

capable of providing up to 20 mA of total current. The array

is divided into 31 equal currents that make up the five most

significant bits (MSBs). The next four bits or middle bits consist

of 15 equal current sources whose value is 1/16th of an MSB

current source. The remaining LSBs are binary weighted frac-

tions of the middle bits current sources. Implementing the

middle and lower bits with current sources, instead of an R-2R

ladder, enhances its dynamic performance for multitone or low

amplitude signals and helps maintain the DAC’s high output

impedance (i.e., >100 kΩ).

All of these current sources are switched to one or the other of

the two output nodes (i.e., I

OUTA

or I

OUTB

) via PMOS differen-

tial current switches. The switches are based on a new architec-

ture that drastically improves distortion performance. This new

switch architecture reduces various timing errors and provides

matching complementary drive signals to the inputs of the dif-

ferential current switches.

The analog and digital sections of the AD9764 have separate

power supply inputs (i.e., AVDD and DVDD) that can operate

independently over a 2.7 volt to 5.5 volt range. The digital

section, which is capable of operating up to a 125 MSPS clock

rate, consists of edge-triggered latches and segment decoding

logic circuitry. The analog section includes the PMOS current

sources, the associated differential switches, a 1.20 V bandgap

voltage reference and a reference control amplifier.

The full-scale output current is regulated by the reference con-

trol amplifier and can be set from 2 mA to 20 mA via an exter-

nal resistor, R

SET

. The external resistor, in combination with

both the reference control amplifier and voltage reference

REFIO

, sets the reference current I

REF

, which is mirrored over to

the segmented current sources with the proper scaling factor.

The full-scale current, I

OUTFS

, is 32 times the value of I

REF

DAC TRANSFER FUNCTION

The AD9764 provides complementary current outputs, I

OUTA

and I

OUTB

. I

OUTA

will provide a near full-scale current output,

OUTFS

, when all bits are high (i.e., DAC CODE = 16383) while

OUTB

, the complementary output, provides no current. The

current output appearing at I

OUTA

and I

OUTB

is a function of

both the input code and I

OUTFS

and can be expressed as:

OUTA

= (DAC CODE/16384) × I

OUTFS

(1)

OUTB

= (16383 – DAC CODE)/16384 × I

OUTFS

(2)

where DAC CODE = 0 to 16383 (i.e., Decimal Representation).

As mentioned previously, I

OUTFS

is a function of the reference

current I

REF

, which is nominally set by a reference voltage

REFIO

and external resistor R

SET

. It can be expressed as:

OUTFS

= 32 × I

REF

(3)

where I

REF

= V

REFIO

SET

(4)

The two current outputs will typically drive a resistive load

directly or via a transformer. If dc coupling is required, I

OUTA

and I

OUTB

should be directly connected to matching resistive

loads, R

LOAD

, that are tied to analog common, ACOM. Note

that R

LOAD

may represent the equivalent load resistance seen by

OUTA

or I

OUTB

as would be the case in a doubly terminated

50 Ω or 75 Ω cable. The single-ended voltage output appearing

at the I

OUTA

and I

OUTB

nodes is simply:

OUTA

= I

OUTA

× R

LOAD

(5)

OUTB

= I

OUTB

× R

LOAD

(6)

Note that the full-scale value of V

OUTA

and V

OUTB

should not

exceed the specified output compliance range to maintain speci-

fied distortion and linearity performance.

The differential voltage, V

DIFF

, appearing across I

OUTA

and

OUTB

is:

DIFF

= (I

OUTA

– I

OUTB

) × R

LOAD

(7)

Substituting the values of I

OUTA

, I

OUTB

and I

REF

; V

DIFF

can be

expressed as:

DIFF

= {(2 DAC CODE – 16383)/16384} ×

DIFF

= {(32 R

LOAD

SET

) × V

REFIO

(8)

These last two equations highlight some of the advantages of

operating the AD9764 differentially. First, the differential op-

eration will help cancel common-mode error sources associated

with I

OUTA

and I

OUTB

such as noise, distortion and dc offsets.

Second, the differential code-dependent current and subsequent

voltage, V

DIFF

, is twice the value of the single-ended voltage

output (i.e., V

OUTA

or V

OUTB

), thus providing twice the signal

power to the load.

Note that the gain drift temperature performance for a single-

ended (V

OUTA

and V

OUTB

) or differential output (V

DIFF

) of the

AD9764 can be enhanced by selecting temperature tracking

resistors for R

LOAD

and R

SET

due to their ratiometric relation-

ship as shown in Equation 8.

DIGITAL DATA INPUTS

(

DB13–DB0

)

50pF

COMP1

+1.20V REF

AVDD ACOM

REFLO

COMP2

PMOS

CURRENT SOURCE

ARRAY

0.1mF

+5V

SEGMENTED SWITCHES

FOR DB13–DB5

LSB

SWITCHES

REFIO

FS ADJ

DVDD

DCOM

CLOCK

+5V

SET

2kV

0.1mF

OUTA

OUTB

0.1mF

AD9764

SLEEP

REF

REFIO

CLOCK

OUTB

OUTA

LOAD

50V

OUTB

OUTA

LOAD

50V

DIFF

= V

OUTA

– V

OUTB

LATCHES

Figure 21. Functional Block Diagram

REV. C

AD9764

–10–

REFERENCE OPERATION

The AD9764 contains an internal 1.20 V bandgap reference

that can be easily disabled and overridden by an external

reference. REFIO serves as either an input or output, depending

on whether the internal or external reference is selected. If

REFLO is tied to ACOM, as shown in Figure 22, the internal

reference is activated, and REFIO provides a 1.20 V output. In

this case, the internal reference must be compensated externally

with a ceramic chip capacitor of 0.1 µF or greater from REFIO

to REFLO. Also, REFIO should be buffered with an external

amplifier having an input bias current less than 100 nA if any

additional loading is required.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1mF

+5V

REFIO

FS ADJ

2kV

0.1mF

AD9764

ADDITIONAL

LOAD

OPTIONAL

EXTERNAL

REF BUFFER

Figure 22. Internal Reference Configuration

The internal reference can be disabled by connecting REFLO to

AVDD. In this case, an external reference may then be applied

to REFIO as shown in Figure 23. The external reference may

provide either a fixed reference voltage to enhance accuracy and

drift performance or a varying reference voltage for gain control.

Note that the 0.1 µF compensation capacitor is not required

since the internal reference is disabled, and the high input im-

pedance (i.e., 1 MΩ) of REFIO minimizes any loading of the

external reference.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

0.1mF

AVDD

REFIO

FS ADJ

SET

AD9764

EXTERNAL

REF

REFIO

SET

AVDD

REFERENCE

CONTROL

AMPLIFIER

REFIO

Figure 23. External Reference Configuration

REFERENCE CONTROL AMPLIFIER

The AD9764 also contains an internal control amplifier that is

used to regulate the DAC’s full-scale output current, I

OUTFS

The control amplifier is configured as a V-I converter, as shown

in Figure 23, such that its current output, I

REF

, is determined by

the ratio of the V

REFIO

and an external resistor, R

SET

, as stated

in Equation 4. I

REF

is copied over to the segmented current

sources with the proper scaling factor to set I

OUTFS

as stated in

Equation 3.

The control amplifier allows a wide (10:1) adjustment span of

OUTFS

over a 2 mA to 20 mA range by setting IREF between

62.5 µA and 625 µA. The wide adjustment span of I

OUTFS

provides several application benefits. The first benefit relates

directly to the power dissipation of the AD9764, which is pro-

portional to I

OUTFS

(refer to the Power Dissipation section). The

second benefit relates to the 20 dB adjustment, which is useful

for system gain control purposes.

The small signal bandwidth of the reference control amplifier is

approximately 1.4 MHz and can be reduced by connecting an

external capacitor between COMP1 and AVDD. The output of

the control amplifier, COMP1, is internally compensated via a

50 pF capacitor that limits the control amplifier small-signal

bandwidth and reduces its output impedance. Any additional

external capacitance further limits the bandwidth and acts as a

filter to reduce the noise contribution from the reference ampli-

fier. Figure 24 shows the relationship between the external

capacitor and the small signal –3 dB bandwidth of the refer-

ence amplifier. Since the –3 dB bandwidth corresponds to the

dominant pole, and hence the time constant, the settling time of

the control amplifier to a stepped reference input response can

be approximated.

COMP1 CAPACITOR – nF

1000

0.1

0.1 10001

BANDWIDTH – kHz

10 100

Figure 24. External COMP1 Capacitor vs. –3 dB Bandwidth

The optimum distortion performance for any reconstructed

waveform is obtained with a 0.1 µF external capacitor installed.

Thus, if I

REF

is fixed for an application, a 0.1 µF ceramic chip

capacitor is recommended. Also, since the control amplifier is

optimized for low power operation, multiplying applications

requiring large signal swings should consider using an external

control amplifier to enhance the application’s overall large signal

multiplying bandwidth and/or distortion performance.

There are two methods in which I

REF

can be varied for a fixed

SET

. The first method is suitable for a single-supply system in

which the internal reference is disabled, and the common-mode

voltage of REFIO is varied over its compliance range of 1.25 V

to 0.10 V. REFIO can be driven by a single-supply amplifier or

DAC, thus allowing I

REF

to be varied for a fixed R

SET

. Since the

input impedance of REFIO is approximately 1 MΩ, a simple,

low cost R-2R ladder DAC configured in the voltage mode

topology may be used to control the gain. This circuit is shown

in Figure 25 using the AD7524 and an external 1.2 V reference,

the AD1580.

REV. C

AD9764

–11–

The second method may be used in a dual-supply system in

which the common-mode voltage of REFIO is fixed, and I

REF

varied by an external voltage, V

, applied to R

SET

via an ampli-

fier. An example of this method is shown in Figure 26 in which

the internal reference is used to set the common-mode voltage

of the control amplifier to 1.20 V. The external voltage, V

, is

referenced to ACOM and should not exceed 1.2 V. The value of

SET

is such that I

REFMAX

and I

REFMIN

do not exceed 62.5 µA

and 625 µA, respectively. The associated equations in Figure 26

can be used to determine the value of R

SET

50pF

COMP1 AVDDREFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9764

REF

OPTIONAL

BANDLIMITING

CAPACITOR

1mF

REF

= (1.2–V

)/R

SET

WITH V

< V

REFIO

AND 62.5mA # I

REF

# 625A

+1.2V REF

Figure 26. Dual-Supply Gain Control Circuit

In some applications, the user may elect to use an external

control amplifier to enhance the multiplying bandwidth,

distortion performance and/or settling time. External amplifiers

capable of driving a 50 pF load such as the AD817 are suitable

for this purpose. It is configured in such a way that it is in

parallel with the weaker internal reference amplifier as shown in

Figure 27. In this case, the external amplifier simply overdrives

the weaker reference control amplifier. Also, since the internal

control amplifier has a limited current output, it will sustain no

damage if overdriven.

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9764

REF

INPUT

EXTERNAL

CONTROL AMPLIFIER

Figure 27. Configuring an External Reference Control

Amplifier

ANALOG OUTPUTS

The AD9764 produces two complementary current outputs,

OUTA

and I

OUTB

, which may be configured for single-end

or differential operation. I

OUTA

and I

OUTB

can be converted into

complementary single-ended voltage outputs, V

OUTA

and

OUTB

, via a load resistor, R

LOAD

, as described in the DAC

Transfer Function section by Equations 5 through 8. The

differential voltage, V

DIFF

, existing between V

OUTA

and V

OUTB

can also be converted to a single-ended voltage via a transformer

or differential amplifier configuration.

Figure 28 shows the equivalent analog output circuit of the

AD9764 consisting of a parallel combination of PMOS differen-

tial current switches associated with each segmented current

source. The output impedance of I

OUTA

and I

OUTB

is determined

by the equivalent parallel combination of the PMOS switches

and is typically 100 kΩ in parallel with 5 pF. Due to the na-

ture of a PMOS device, the output impedance is also slightly

dependent on the output voltage (i.e., V

OUTA

and V

OUTB

) and, to

a lesser extent, the analog supply voltage, AVDD, and full-scale

current, I

OUTFS

. Although the output impedance’s signal depen-

dency can be a source of dc nonlinearity and ac linearity (i.e.,

distortion), its effects can be limited if certain precautions are

noted.

AD9764

AVDD

OUTA

OUTB

LOAD

Figure 28. Equivalent Analog Output Circuit

OUTA

and I

OUTB

also have a negative and positive voltage compli-

ance range. The negative output compliance range of –1.0 V is

set by the breakdown limits of the CMOS process. Operation

beyond this maximum limit may result in a breakdown of the

output stage and affect the reliability of the AD9764. The posi-

tive output compliance range is slightly dependent on the full-

scale output current, I

OUTFS

. It degrades slightly from its nominal

1.2V

50pF

COMP1

+1.2V REF

AVDD

REFLO

CURRENT

SOURCE

ARRAY

AVDD

REFIO

FS ADJ

SET

AD9764

REF

SET

AVDD

OPTIONAL

BANDLIMITING

CAPACITOR

REF

OUT1

OUT2

AGND

DB7–DB0

AD7524

AD1580

0.1V TO 1.2V

Figure 25. Single-Supply Gain Control Circuit

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P23

AD9764ARU

Mfr. #:

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Digital to Analog Converters - DAC 14-Bit 100 MSPS

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