REV. C
AD9764
–6–
DEFINITIONS OF SPECIFICATIONS
Linearity Error (Also Called Integral Nonlinearity or INL)
Linearity error is defined as the maximum deviation of the
actual analog output from the ideal output, determined by a
straight line drawn from zero to full scale.
Differential Nonlinearity (or DNL)
DNL is the measure of the variation in analog value, normalized
to full scale, associated with a 1 LSB change in digital input
code.
Offset Error
The deviation of the output current from the ideal of zero is
called offset error. For I
OUTA
, 0 mA output is expected when the
inputs are all 0s. For I
OUTB
, 0 mA output is expected when all
inputs are set to 1s.
Gain Error
The difference between the actual and ideal output span. The
actual span is determined by the output when all inputs are set
to 1s minus the output when all inputs are set to 0s.
Output Compliance Range
The range of allowable voltage at the output of a current-output
DAC. Operation beyond the maximum compliance limits may
cause either output stage saturation or breakdown, resulting in
nonlinear performance.
Temperature Drift
Temperature drift is specified as the maximum change from the
ambient (+25°C) value to the value at either T
MIN
or T
MAX
. For
offset and gain drift, the drift is reported in ppm of full-scale
range (FSR) per degree C. For reference drift, the drift is
reported in ppm per degree C.
Power Supply Rejection
The maximum change in the full-scale output as the supplies
are varied over a specified range.
Settling Time
The time required for the output to reach and remain within a
specified error band about its final value, measured from the
start of the output transition.
Glitch Impulse
Asymmetrical switching times in a DAC give rise to undesired
output transients that are quantified by a glitch impulse. It is
specified as the net area of the glitch in pV-s.
Spurious-Free Dynamic Range
The difference, in dB, between the rms amplitude of the output
signal and the peak spurious signal over the specified bandwidth.
Total Harmonic Distortion
THD is the ratio of the sum of the rms value of the first six
harmonic components to the rms value of the measured output
signal. It is expressed as a percentage or in decibels (dB).
Multitone Power Ratio
The spurious-free dynamic range for an output containing mul-
tiple carrier tones of equal amplitude. It is measured as the
difference between the rms amplitude of a carrier tone to the
peak spurious signal in the region of a removed tone.
50pF
COMP1
+1.20V REF
AVDD ACOM
REFLO
COMP2
PMOS
CURRENT SOURCE
ARRAY
0.1mF
SEGMENTED SWITCHES
FOR DB13–DB5
LSB
SWITCHES
REFIO
FS ADJ
DVDD
DCOM
CLOCK
+5V
R
SET
2kV
0.1mF
DVDD
DCOM
I
OUTA
I
OUTB
0.1mF
AD9764
SLEEP
50V
RETIMED
CLOCK
OUTPUT*
LATCHES
DIGITAL
DATA
TEKTRONIX
AWG-2021
LECROY 9210
PULSE GENERATOR
CLOCK
OUTPUT
50V
20pF
50V
20pF
100V
TO HP3589A
SPECTRUM/
NETWORK
ANALYZER
50V INPUT
MINI-CIRCUITS
T1-1T
* AWG2021 CLOCK RETIMED
SUCH THAT DIGITAL DATA
TRANSITIONS ON FALLING EDGE
OF 50% DUTY CYCLE CLOCK.
+5V
Figure 2. Basic AC Characterization Test Setup
REV. C
AD9764
–7–
Typical AC Characterization Curves
(AVDD = +5 V, DVDD = +3 V, I
OUTFS
= 20 mA, 50 Doubly Terminated Load, Differential Output, T
A
= +25C, SFDR up to Nyquist, unless otherwise noted)
FREQUENCY – MHz
SFDR – dBc
90
85
40
0.1 1 10010
55
45
50
65
60
80
70
75
5 MSPS
25 MSPS
50 MSPS
100 MSPS
Figure 3. SFDR vs. f
OUT
@ 0 dBFS
FREQUENCY – MHz
SFDR – dBc
90
85
40
05 25
10 15 20
60
55
50
45
80
70
75
65
0dBFS
–6dBFS
–12dBFS
Figure 6. SFDR vs. f
OUT
@ 50 MSPS
A
OUT
– dBFS
SFDR – dBc
90
80
50
–30 –25 0–20 –15 –10 5
70
60
455kHz @ 5 MSPS
2.27MHz @ 25 MSPS
4.55MHz @ 50 MSPS
9.09MHz @ 100 MSPS
Figure 9. Single-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/11
FREQUENCY – MHz
SFDR – dBc
90
85
40
0 0.5 2.5
1.0 1.5 2.0
60
55
50
45
80
70
75
65
0dBFS
–6dBFS
–12dBFS
Figure 4. SFDR vs. f
OUT
@ 5 MSPS
FREQUENCY – MHz
SFDR – dBc
90
85
40
010 5020 30 40
60
55
50
45
80
70
75
65
0dBFS
–6dBFS
–12dBFS
Figure 7. SFDR vs. f
OUT
@100 MSPS
A
OUT
– dBFS
SFDR – dBc
90
80
50
–30 –25 0–20 –15 –10 5
70
60
1MHz @ 5 MSPS
5MHz @ 25 MSPS
10MHz @ 50 MSPS
20MHz @ 100 MSPS
Figure 10. Single-Tone SFDR vs.
A
OUT
@ f
OUT
= f
CLOCK
/5
FREQUENCY – MHz
SFDR – dBc
90
40
02 1246810
85
60
55
50
45
80
75
65
70
0dBFS
–6dBFS
–12dBFS
Figure 5. SFDR vs. f
OUT
@ 25 MSPS
Figure 8. SFDR vs. f
OUT
and
I
OUTFS
@ 25 MSPS and 0 dBFS
A
OUT
– dBFS
SFDR – dBc
90
80
50
–30 –25 0
–20 –15 –10 –5
70
60
0.675/0.725MHz @ 5 MSPS
3.38/3.63MHz @ 25 MSPS
13.5/14.5MHz @ 100 MSPS
6.75/7.25 @ 50 MSPS
Figure 11. Dual-Tone SFDR vs. A
OUT
@ f
OUT
= f
CLOCK
/7
REV. C
AD9764
–8–
dBc
–70
–75
–95
000.0E+0 40.0E+6 80.0E+6 120.0E+6
–80
–85
–90
2ND HARMONIC
3RD HARMONIC
4TH HARMONIC
Figure 12. THD vs. f
CLOCK
@
f
OUT
= 2 MHz
CODE
ERROR – LSB
2.0
–2.0
0 160004000 8000 12000
1.5
0.0
–0.5
–1.0
–1.5
1.0
0.5
Figure 15. Typical INL
000.0E+0 7.5E+6 15.0E+6 22.5E+6
10dB – Div
0
–10
–90
–50
–60
–70
–80
–20
–40
–30
f
CLK
= 50MSPS
f
OUT
= 1.25MHz
SFDR = 78dBc
AMPLITUDE = 0dBFS
Figure 18. Single-Tone SFDR
f
CLOCK
– MSPS
SNR – dB
85
80
60
0 10 100
20 30 40 50 60 70 80 90
75
70
65
I
OUTFS
= 5mA,
DVDD = +5V
I
OUTFS
= 5mA,
DVDD = +3V
I
OUTFS
= 10mA,
DVDD = +5V
I
OUTFS
= 10mA,
DVDD = +3V
I
OUTFS
= 20mA,
DVDD = +5V
I
OUTFS
= 20mA,
DVDD = +3V
Figure 13. SNR vs. f
CLOCK
@ f
OUT
=
2.0 MHz
CODE
ERROR – LSB
2.0
–1.0
0 16000
4000 8000 12000
1.5
1.0
0.5
0.0
–0.5
Figure 16. Typical DNL
0E+0 25E+65E+6 10E+6 15E+6 20E+6
10dB – Div
0
–10
–90
–50
–60
–70
–80
–20
–40
–30
f
CLK
= 50MSPS
f
OUT1
= 6.75MHz
f
OUT2
= 7.25MHz
SFDR = 69dBc
AMPLITUDE = 0dBFS
Figure 19. Dual-Tone SFDR
OUTPUT FREQUENCY – MHz
SFDR – dBc
80
70
50
1 10 100
60
I
DIFF
@ 0dBFS
I
DIFF
@ –6dBFS
I
A
@ 0dBFS
I
A
@ –6dBFS
Figure 14. Differential vs. Single-
Ended SFDR vs. f
OUT
@ 50 MSPS
TEMPERATURE – 8C
SFDR – dBc
80
75
50
–40 –20 80
60
70
65
60
55
40200
2.5MHz
10MHz
40MHz
Figure 17. SFDR vs. Temperature
@ 100 MSPS, 0 dBFS
10dB – Div
0
–70
–100
–10
–60
–80
–90
–40
–50
–20
–30
000.0E+0 7.5E+6 15.0E+6 22.5E+6
f
CLK
= 50MSPS
f
OUT1
= 6.25MHz
f
OUT2
= 6.75MHz
f
OUT3
= 7.25MHz
f
OUT4
= 7.75MHz
SFDR = 66dBc
AMPLITUDE = 0dBFS
Figure 20. Four-Tone SFDR

AD9764ARU

Mfr. #:
Manufacturer:
Analog Devices Inc.
Description:
Digital to Analog Converters - DAC 14-Bit 100 MSPS
Lifecycle:
New from this manufacturer.
Delivery:
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