AD9764ARU Datasheet AD9764ARUZ, AD9764ARZ, AD9764AR | P13-P15

REV. C

AD9764

–12–

1.25 V for an I

OUTFS

= 20 mA to 1.00 V for an I

OUTFS

= 2 mA.

Operation beyond the positive compliance range will induce

clipping of the output signal which severely degrades the

AD9764’s linearity and distortion performance.

For applications requiring the optimum dc linearity, I

OUTA

and/

or I

OUTB

should be maintained at a virtual ground via an I-V op

amp configuration. Maintaining I

OUTA

and/or I

OUTB

at a virtual

ground keeps the output impedance of the AD9764 fixed, signifi-

cantly reducing its effect on linearity. However, it does not

necessarily lead to the optimum distortion performance due to

limitations of the I-V op amp. Note that the INL/DNL speci-

fications for the AD9764 are measured in this manner using

OUTA

. In addition, these dc linearity specifications remain

virtually unaffected over the specified power supply range of

2.7 V to 5.5 V.

Operating the AD9764 with reduced voltage output swings at

OUTA

and I

OUTB

in a differential or single-ended output configu-

ration reduces the signal dependency of its output impedance

thus enhancing distortion performance. Although the voltage

compliance range of I

OUTA

and I

OUTB

extends from –1.0 V to

+1.25 V, optimum distortion performance is achieved when the

maximum full-scale signal at I

OUTA

and I

OUTB

does not exceed

approximately 0.5 V. A properly selected transformer with a

grounded center-tap will allow the AD9764 to provide the re-

quired power and voltage levels to different loads while main-

taining reduced voltage swings at I

OUTA

and I

OUTB

. DC-coupled

applications requiring a differential or single-ended output con-

figuration should size R

LOAD

accordingly. Refer to Applying the

AD9764 section for examples of various output configurations.

The most significant improvement in the AD9764’s distortion

and noise performance is realized using a differential output

configuration. The common-mode error sources of both I

OUTA

and I

OUTB

can be substantially reduced by the common-mode

rejection of a transformer or differential amplifier. These

common-mode error sources include even-order distortion

products and noise. The enhancement in distortion performance

becomes more significant as the reconstructed waveform’s

frequency content increases and/or its amplitude decreases.

This is evident in Figure 14, which compares the differential

vs. single-ended performance of the AD9764 at 50 MSPS for

0.0 and –6.0 dBFS single tone waveforms over frequency.

The distortion and noise performance of the AD9764 is also

slightly dependent on the analog and digital supply as well as the

full-scale current setting, I

OUTFS

. Operating the analog supply at

5.0 V ensures maximum headroom for its internal PMOS current

sources and differential switches leading to improved distortion

performance as shown in Figure 8. Although I

OUTFS

can be set

between 2 mA and 20 mA, selecting an I

OUTFS

of 20 mA will

provide the best distortion and noise performance also shown in

Figure 8. The noise performance of the AD9764 is affected by

the digital supply (DVDD), output frequency, and increases

with increasing clock rate as shown in Figure 13. Operating the

AD9764 with low voltage logic levels between 3 V and 3.3 V

will slightly reduce the amount of on-chip digital noise.

In summary, the AD9764 achieves the optimum distortion and

noise performance under the following conditions:

(1) Differential Operation.

(2) Positive voltage swing at I

OUTA

and I

OUTB

limited to +0.5 V.

(3) I

OUTFS

set to 20 mA.

(4) Analog Supply (AVDD) set at 5.0 V.

(5) Digital Supply (DVDD) set at 3.0 V to 3.3 V with appro-

priate logic levels.

Note that the ac performance of the AD9764 is characterized

under the above mentioned operating conditions.

DIGITAL INPUTS

The AD9764’s digital input consists of 14 data input pins and a

clock input pin. The 14-bit parallel data inputs follow standard

positive binary coding where DB13 is the most significant bit

(MSB), and DB0 is the least significant bit (LSB). I

OUTA

pro-

duces a full-scale output current when all data bits are at Logic

1. I

OUTB

produces a complementary output with the full-scale

current split between the two outputs as a function of the input

code.

The digital interface is implemented using an edge-triggered

master slave latch. The DAC output is updated following the

rising edge of the clock as shown in Figure 1 and is designed to

support a clock rate as high as 125 MSPS. The clock can be

operated at any duty cycle that meets the specified latch pulse-

width. The setup and hold times can also be varied within the

clock cycle as long as the specified minimum times are met,

although the location of these transition edges may affect digital

feedthrough and distortion performance. Best performance is

typically achieved when the input data transitions on the falling

edge of a 50% duty cycle clock.

The digital inputs are CMOS-compatible with logic thresholds,

THRESHOLD,

set to approximately half the digital positive supply

(DVDD) or

THRESHOLD

= DVDD/2 (±20%)

The internal digital circuitry of the AD9764 is capable of operating

over a digital supply range of 2.7 V to 5.5 V. As a result, the

digital inputs can also accommodate TTL levels when DVDD is

set to accommodate the maximum high level voltage of the TTL

drivers V

OH(MAX)

. A DVDD of 3 V to 3.3 V will typically ensure

proper compatibility with most TTL logic families. Figure 29

shows the equivalent digital input circuit for the data and clock

inputs. The sleep mode input is similar with the exception that

it contains an active pull-down circuit, thus ensuring that the

AD9764 remains enabled if this input is left disconnected.

DVDD

DIGITAL

INPUT

Figure 29. Equivalent Digital Input

REV. C

AD9764

–13–

Since the AD9764 is capable of being updated up to 125 MSPS,

the quality of the clock and data input signals are important in

achieving the optimum performance. Operating the AD9764

with reduced logic swings and a corresponding digital supply

(DVDD) will result in the lowest data feedthrough and on-chip

digital noise. The drivers of the digital data interface circuitry

should be specified to meet the minimum setup and hold times

of the AD9764 as well as its required min/max input logic level

thresholds.

Digital signal paths should be kept short and run lengths

matched to avoid propagation delay mismatch. The insertion

of a low value resistor network (i.e., 20 Ω to 100 Ω) between

the AD9764 digital inputs and driver outputs may be helpful in

reducing any overshooting and ringing at the digital inputs that

contribute to data feedthrough. For longer run lengths and high

data update rates, strip line techniques with proper termination

resistors should be considered to maintain “clean” digital inputs.

The external clock driver circuitry should provide the AD9764

with a low jitter clock input meeting the min/max logic levels

while providing fast edges. Fast clock edges will help minimize

any jitter that will manifest itself as phase noise on a recon-

structed waveform. Thus, the clock input should be driven by

the fastest logic family suitable for the application.

Note, that the clock input could also be driven via a sine wave,

which is centered around the digital threshold (i.e., DVDD/2)

and meets the min/max logic threshold. This will typically result

in a slight degradation in the phase noise, which becomes more

noticeable at higher sampling rates and output frequencies.

Also, at higher sampling rates, the 20% tolerance of the digital

logic threshold should be considered since it will affect the effec-

tive clock duty cycle and, subsequently, cut into the required

data setup and hold times.

SLEEP MODE OPERATION

The AD9764 has a power-down function that turns off the

output current and reduces the supply current to less than

8.5 mA over the specified supply range of 2.7 V to 5.5 V and

temperature range. This mode can be activated by applying a

logic level “1” to the SLEEP pin. This digital input also con-

tains an active pull-down circuit that ensures the AD9764 re-

mains enabled if this input is left disconnected. The SLEEP

input with active pull-down requires <40 µA of drive current.

The power-up and power-down characteristics of the AD9764

are dependent upon the value of the compensation capacitor

connected to COMP1. With a nominal value of 0.1 µF, the

AD9764 takes less than 5 µs to power down and approximately

3.25 ms to power back up. Note, the SLEEP MODE should not

be used when the external control amplifier is used as shown in

Figure 27.

POWER DISSIPATION

The power dissipation, P

, of the AD9764 is dependent on

several factors, including: (1) AVDD and DVDD, the power

supply voltages; (2) I

OUTFS

, the full-scale current output; (3)

CLOCK

, the update rate; and (4) the reconstructed digital input

waveform. The power dissipation is directly proportional to the

analog supply current, I

AVDD

, and the digital supply current,

DVDD

. I

AVDD

is directly proportional to I

OUTFS,

as shown in

Figure 30, and is insensitive to f

CLOCK

OUTFS

– mA

2204 6 8 10 12141618

AVDD

– mA

Figure 30. I

AVDD

vs. I

OUTFS

Conversely, I

DVDD

is dependent on both the digital input wave-

form, f

CLOCK

, and digital supply DVDD. Figures 31 and 32

show I

DVDD

as a function of full-scale sine wave output ratios

OUT

CLOCK

) for various update rates with DVDD = 5 V and

DVDD = 3 V, respectively. Note, how I

DVDD

is reduced by more

than a factor of 2 when DVDD is reduced from 5 V to 3 V.

RATIO – f

OUT

CLK

0.01 10.1

DVDD

– mA

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 31. I

DVDD

vs. Ratio @ DVDD = 5 V

RATIO – f

OUT

CLK

0.01 10.1

DVDD

– mA

5MSPS

25MSPS

50MSPS

100MSPS

125MSPS

Figure 32. I

DVDD

vs. Ratio @ DVDD = 3 V

REV. C

AD9764

–14–

APPLYING THE AD9764

OUTPUT CONFIGURATIONS

The following sections illustrate some typical output configura-

tions for the AD9764. Unless otherwise noted, it is assumed

that I

OUTFS

is set to a nominal 20 mA. For applications requir-

ing the optimum dynamic performance, a differential output

configuration is suggested. A differential output configuration

may consist of either an RF transformer or a differential op amp

configuration. The transformer configuration provides the opti-

mum high frequency performance and is recommended for any

application allowing for ac coupling. The differential op amp

configuration is suitable for applications requiring dc coupling, a

bipolar output, signal gain and/or level shifting.

A single-ended output is suitable for applications requiring a

unipolar voltage output. A positive unipolar output voltage will

result if I

OUTA

and/or I

OUTB

is connected to an appropriately

sized load resistor, R

LOAD

, referred to ACOM. This configura-

tion may be more suitable for a single-supply system requiring a

dc coupled, ground referred output voltage. Alternatively, an

amplifier could be configured as an I-V converter, thus convert-

ing I

OUTA

or I

OUTB

into a negative unipolar voltage. This con-

figuration provides the best dc linearity since I

OUTA

or I

OUTB

maintained at a virtual ground. Note, I

OUTA

provides slightly

better performance than I

OUTB

DIFFERENTIAL COUPLING USING A TRANSFORMER

An RF transformer can be used to perform a differential-to-

single-ended signal conversion as shown in Figure 33. A

differentially coupled transformer output provides the optimum

distortion performance for output signals whose spectral content

lies within the transformer’s passband. An RF transformer such

as the Mini-Circuits T1-1T provides excellent rejection of com-

mon-mode distortion (i.e., even-order harmonics) and noise

over a wide frequency range. It also provides electrical isolation

and the ability to deliver twice the power to the load. Trans-

formers with different impedance ratios may also be used for

impedance matching purposes. Note that the transformer

provides ac coupling only.

LOAD

AD9764

MINI-CIRCUITS

T1-1T

OPTIONAL R

DIFF

OUTA

OUTB

Figure 33. Differential Output Using a Transformer

The center tap on the primary side of the transformer must be

connected to ACOM to provide the necessary dc current path

for both I

OUTA

and I

OUTB

. The complementary voltages appear-

ing at I

OUTA

and I

OUTB

(i.e., V

OUTA

and V

OUTB

) swing sym-

metrically around ACOM and should be maintained with the

specified output compliance range of the AD9764. A differential

resistor, R

DIFF

, may be inserted in applications in which the

output of the transformer is connected to the load, R

LOAD

, via a

passive reconstruction filter or cable. R

DIFF

is determined by the

transformer’s impedance ratio and provides the proper source

termination that results in a low VSWR. Note that approxi-

mately half the signal power will be dissipated across R

DIFF

DIFFERENTIAL USING AN OP AMP

An op amp can also be used to perform a differential-to-single-

ended conversion as shown in Figure 34. The AD9764 is con-

figured with two equal load resistors, R

LOAD

, of 25 Ω. The

differential voltage developed across I

OUTA

and I

OUTB

is con-

verted to a single-ended signal via the differential op amp con-

figuration. An optional capacitor can be installed across I

OUTA

and I

OUTB

, forming a real pole in a low-pass filter. The addition

of this capacitor also enhances the op amp’s distortion perfor-

mance by preventing the DAC’s high slewing output from over-

loading the op amp’s input.

AD9764

OUTA

OUTB

OPT

500V

225V

500V

25V25V

AD8047

Figure 34. DC Differential Coupling Using an Op Amp

The common-mode rejection of this configuration is typically

determined by the resistor matching. In this circuit, the differ-

ential op amp circuit using the AD8047 is configured to provide

some additional signal gain. The op amp must operate from a

dual supply since its output is approximately ±1.0 V. A high

speed amplifier capable of preserving the differential perform-

ance of the AD9764 while meeting other system level objectives

(i.e., cost, power) should be selected. The op amps differential

gain, its gain setting resistor values and full-scale output swing

capabilities should all be considered when optimizing this circuit.

The differential circuit shown in Figure 35 provides the neces-

sary level-shifting required in a single supply system. In this

case, AVDD, which is the positive analog supply for both the

AD9764 and the op amp, is also used to level-shift the differ-

ential output of the AD9764 to midsupply (i.e., AVDD/2). The

AD8041 is a suitable op amp for this application.

AD9764

OUTA

OUTB

OPT

500V

225V

1kV

25V25V

AD8041

1kV

AVDD

Figure 35. Single-Supply DC Differential Coupled Circuit

SINGLE-ENDED UNBUFFERED VOLTAGE OUTPUT

Figure 36 shows the AD9764 configured to provide a unipolar

output range of approximately 0 V to +0.5 V for a doubly termi-

nated 50 Ω cable since the nominal full-scale current, I

OUTFS

, of

20 mA flows through the equivalent R

LOAD

of 25 Ω. In this case,

LOAD

represents the equivalent load resistance seen by I

OUTA

OUTB

. The unused output (I

OUTA

or I

OUTB

) can be connected to

ACOM directly or via a matching R

LOAD

. Different values of

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AD9764ARU

Mfr. #:

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Manufacturer:

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Description:

Digital to Analog Converters - DAC 14-Bit 100 MSPS

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