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ATF-511P8-TR1

P1-P3P4-P6P7-P9P10-P12P13-P15
ATF-511P8
High Linearity Enhancement Mode
[1]
Pseudomorphic HEMT
in 2x2 mm
2
LPCC
[3]
Package
Data Sheet
Pin Connections and Package Marking
Note:
Package marking provides orientation and identi cation:
“1P” = Device Code
“x” = Date code indicates the month of manufacture.
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Pin 8
Pin 7 (Drain)
Pin 6
Pin 5
1Px
Top View
Pin 8
Source
(Thermal/RF Gnd)
Pin 7 (Drain)
Pin 6
Pin 5
Pin 1 (Source)
Pin 2 (Gate)
Pin 3
Pin 4 (Source)
Bottom View
Features
Single voltage operation
High linearity and P1dB
Low noise  gure
Excellent uniformity in product speci cations
Small package size:
2.0 x 2.0 x 0.75 mm
Point MTTF > 300 years
[2]
MSL-1 and lead-free
Tape-and-reel packaging option available
Speci cations
2 GHz; 4.5V, 200 mA (Typ.)
41.7 dBm output IP3
30 dBm output power at 1 dB gain compression
1.4 dB noise  gure
14.8 dB gain
12.1 dB LFOM
[4]
69% PAE
Applications
Front-end LNA Q2 and Q3 driver or pre-driver ampli er
for Cellular/PCS and WCDMA wireless infrastructure
Driver ampli er for WLAN, WLL/RLL and MMDS
applications
General purpose discrete E-pHEMT for other high
linearity applications
Description
Avago Technologies’s ATF-511P8 is a single-voltage high
linearity, low noise E-pHEMT housed in an 8-lead JEDEC-
standard leadless plastic chip carrier (LPCC
[3]
) package.
The device is ideal as a high linearity, low-noise, medium-
power ampli er. Its operating frequency range is from 50
MHz to 6 GHz.
The thermally e cient package measures only 2 mm
x 2 mm x 0.75 mm. Its backside metalization provides
excellent thermal dissipation as well as visual evidence
of solder re ow. The device has a Point MTTF of over 300
years at a mounting temperature of +85°C. All devices
are 100% RF & DC tested.
Notes:
1. Enhancement mode technology employs a single positive V
gs
,
eliminating the need of negative gate voltage associated with
conventional depletion mode devices.
2. Refer to reliability datasheet for detailed MTTF data.
3. Conforms to JEDEC reference outline MO229 for DRP-N.
4. Linearity Figure of Merit (LFOM) is essentially OIP3 divided by DC
bias power.
2
ATF-511P8 Absolute Maximum Ratings
[1]
Absolute
Symbol Parameter Units Maximum
V
DS
Drain–Source Voltage
[2]
V 7
V
GS
Gate –Source Voltage
[2]
V -5 to 1
V
GD
Gate Drain Voltage
[2]
V -5 to 1
I
DS
Drain Current
[2]
A 1
I
GS
Gate Current mA 46
P
diss
Total Power Dissipation
[3]
W 3
P
in max.
RF Input Power
[4]
dBm +30
T
CH
Channel Temperature °C 150
T
STG
Storage Temperature °C -65 to 150

ch_b
Thermal Resistance
[5]
°C/W 33
Notes:
1. Operation of this device in excess of any one
of these parameters may cause permanent
damage.
2. Assumes DC quiescent conditions.
3. Board (package belly) temperatureT
B
is
25°C. Derate 30 mW/°C for T
B
> 50°C.
4. With 10 Ohm series resistor in gate supply
and 3:1 VSWR.
5. Channel-to-board thermal resistance
measured using 150°C Liquid Crystal
Measurement method.
6. Device can safely handle +30dBm RF Input
Power provided I
GS
limited to 46mA. I
GS
at
P
1dB
drive level is bias circuit dependent.
Product Consistency Distribution Charts at 2 GHz, 4.5V, 200 mA
[6,7]
OIP3 (dBm)
Figure 2. OIP3 LSL = 38.5, Nominal = 41.7.
35 41
38
44 47
240
200
160
120
80
40
0
Cpk = 1.66
Stdev = 0.6
-3 Std
+3 Std
P1dB (dBm)
Figure 3. P1dB LSL = 28.5, Nominal = 30.
28 30
29
31
200
160
120
80
40
0
Cpk = 3.24
Stdev = 0.15
-3 Std +3 Std
GAIN (dB)
Figure 4. Gain LSL = 13.5,
Nominal = 14.8, USL = 16.5.
13 15
14
16 17
150
120
90
60
30
0
Cpk = 1.4
Stdev = 0.31
-3 Std +3 Std
Notes:
6. Distribution data sample size is 400 samples taken from 4 di erent
wafers and 3 di erent lots. Future wafers allocated to this product
may have nominal values anywhere between the upper and lower
limits.
Figure 1. Typical I-V Curves (V
gs
= 0.1 per step).
V
DS
(V)
1000
900
800
700
600
500
400
300
200
100
0
02 468
I
DS
(mA)
0.8 V
0.7 V
0.5 V
0.6 V
PAE (%)
Figure 5. PAE LSL = 52, Nominal = 68.9.
52 62
57
67 72 77 82
160
120
80
40
0
Cpk = 3.03
Stdev = 1.85
-3 Std +3 Std
7. Measurements are made on production test board, which represents
a trade-o between optimal OIP3, P1dB and VSWR. Circuit losses
have been de-embedded from actual measurements.
3
ATF-511P8 Electrical Speci cations
T
A
= 25°C, DC bias for RF parameters is Vds = 4.5V and Ids = 200 mA unless otherwise speci ed.
Symbol Parameter and Test Condition Units Min. Typ. Max.
Vgs
Operational Gate Voltage Vds = 4.5V, Ids = 200 mA V 0.25 0.51 0.8
Vth
Threshold Voltage Vds = 4.5V, Ids = 32 mA V — 0.28 —
Idss
Saturated Drain Current Vds = 4.5V, Vgs = 0V μA — 16.4 —
Gm
Transconductance Vds = 4.5V, Gm = Idss/Vgs; mmho — 2178 —
 Vgs = Vgs1 – Vgs2
Vgs1 = 0.55V, Vgs2 = 0.5V
Igss Gate Leakage Current Vds = 0V, Vgs = -4.5V μA -27 -2 —
NF Noise Figure
[1]
f = 2 GHz dB — 1.4 —
f = 900 MHz dB — 1.2 —
G Gain
[1]
f = 2 GHz dB 13.5 14.8 16.5
f = 900 MHz dB — 17.8 —
OIP3
Output 3
rd
Order Intercept Point
[1,2]
f = 2 GHz dBm 38.5 41.7 —
f = 900 MHz dBm — 43 —
P1dB
Output 1dB Compressed
[1]
f = 2 GHz dBm 28.5 30 —
f = 900 MHz dBm — 29.6 —
PAE Power Added E ciency f = 2 GHz % 52 68.9 —
f = 900 MHz % — 68.6 —
ACLR Adjacent Channel Leakage O set BW = 5 MHz dBc — -58.9 —
Power Ratio
[1,3]
O set BW = 10 MHz dBc — -62.7 —
Notes:
1. Measurements obtained using production test board described in Figure 6 and PAE tested at P1dB condition.
2. I ) 2 GHz OIP3 test condition: F1 = 2.0 GHz, F2 = 2.01 GHz and Pin = -5 dBm per tone.
II ) 900 MHz OIP3 test condition: F1 = 900 MHz, F2 = 910 MHz and Pin = -5 dBm per tone.
3. ACLR test spec is based on 3GPP TS 25.141 V5.3.1 (2002-06)
- Test Model 1
- Active Channels: PCCPCH + SCH + CPICH + PICH + SCCPCH + 64 DPCH (SF=128)
- Freq = 2140 MHz
- Pin = -5 dBm
- Channel Integrate Bandwidth = 3.84 MHz
4. Use proper bias, board, heatsink and derating designs to ensure maximum channel temperature is not exceeded. See absolute maximum
ratings and application note for more details.
Input
50 Ohm
Transmission
Line and
Gate Bias T
(0.3 dB loss)
Input
Matching Circuit
Γ_mag = 0.69
Γ_ang = -164°
(1.1 dB loss)
Output
Matching Circuit
Γ_mag = 0.65
Γ_ang = -163°
(0.9 dB loss)
DUT
50 Ohm
Transmission
Line and
Drain Bias T
(0.3 dB loss)
Output
Figure 6. Block diagram of the 2 GHz production test board used for NF, Gain, OIP3 , P1dB and PAE and ACLR measurements. This circuit achieves a trade-
o between optimal OIP3, P1dB and VSWR. Circuit losses have been de-embedded from actual measurements.
P1-P3P4-P6P7-P9P10-P12P13-P15

ATF-511P8-TR1

Mfr. #:
Buy ATF-511P8-TR1
Manufacturer:
Broadcom / Avago
Description:
RF JFET Transistors Transistor GaAs High Linearity
Lifecycle:
New from this manufacturer.
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