2
AT49BV/LV3218(T)
2452F–FLASH–10/02
Note: *Either pin 13 or pin 14 (TSOP package) or ball B3 or ball C4 (CBGA package) can be connected to V
PP
or both pins can be
unconnected.
The device powers on in the read mode. Command sequences are used to place the
device in other operation modes such as program and erase. The device has the capa-
bility to protect the data in any sector (see Sector Lockdown section).
The device is segmented into two memory planes. Reads from memory plane B may be
performed even while program or erase functions are being executed in memory plane
A and vice versa. This operation allows improved system performance by not requiring
the system to wait for a program or erase operation to complete before a read is per-
formed. To further increase the flexibility of the device, it contains an Erase Suspend
feature. This feature will put the erase on hold for any amount of time and let the user
read data from or program data to any of the remaining sectors within the same memory
plane. There is no reason to suspend the erase operation if the data to be read is in the
other memory plane. The end of a program or an erase cycle is detected by the
Ready/Busy
pin, Data Polling or by the toggle bit.
A six-byte command (Enter Single Pulse Program Mode) sequence to remove the
requirement of entering the three-byte program sequence is offered to further improve
programming time. After entering the six-byte code, only single pulses on the write con-
trol lines are required for writing into the device. This mode (Single Pulse Byte/Word
Program) is exited by powering down the device, or by pulsing the RESET
pin low for a
minimum of 500 ns and then bringing it back to V
CC
. Erase and Erase Suspend/Resume
commands will not work while in this mode; if entered they will result in data being pro-
grammed into the device. It is not recommended that the six-byte code reside in the
software of the final product but only exist in external programming code.
The BYTE
pin controls whether the device data I/O pins operate in the byte or word con-
figuration. If the BYTE
pin is set at logic “1”, the device is in word configuration, I/O0 -
I/O15 are active and controlled by CE
and OE.IftheBYTEpin is set at logic “0”, the
device is in byte configuration, and only data I/O pins I/O0 - I/O7 are active and con-
trolled by CE
and OE. The data I/O pins I/O8 - I/O14 are tri-stated, and the I/O15 pin is
used as an input for the LSB (A-1) address function.
CBGA Top View
A
B
C
D
E
F
G
H
A3
A4
A2
A1
A0
CE
OE
VSS
A7
A17
A6
A5
I/O0
I/O8
I/O9
I/O1
RDY/BUSY
NC*
A18
A20
I/O2
I/O10
I/O11
I/O3
WE
RESET
VPP*
A19
I/O5
I/O12
VCC
I/O4
A9
A8
A10
A11
I/O7
I/O14
I/O13
I/O6
A13
A12
A14
A15
A16
BYTE
I/O15/A-1
VSS
1
2
3456
TSOP Top View
Type 1
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
A15
A14
A13
A12
A11
A10
A9
A8
A19
A20
WE
RESET
VPP*
NC*
RDY/BUSY
A18
A17
A7
A6
A5
A4
A3
A2
A1
A16
BYTE
GND
I/O15/A-1
I/O7
I/O14
I/O6
I/O13
I/O5
I/O12
I/O4
VCC
I/O11
I/O3
I/O10
I/O2
I/O9
I/O1
I/O8
I/O0
OE
GND
CE
A0
