16
AT49BV/LV3218(T)
2452F–FLASH–10/02
AC Byte/Word Load Characteristics
AC Byte/Word Load Waveforms
WE Controlled
CE
Controlled
Symbol Parameter Min Max Units
t
AS
,t
OES
Address, OE Setup Time 0 ns
t
AH
Address Hold Time 90 ns
t
CS
Chip Select Setup Time 0 ns
t
CH
Chip Select Hold Time 0 ns
t
WP
Write Pulse Width (WE or CE)50ns
t
DS
Data Setup Time 50 ns
t
DH
,t
OEH
Data, OE Hold Time 0 ns
t
WPH
Write Pulse Width High 35 ns
17
AT49BV/LV3218(T)
2452F–FLASH–10/02
Program Cycle Waveforms
Program Cycle Characteristics
Symbol Parameter Min Typ Max Units
t
BP
Byte/Word Programming Time 15 20 µs
t
AS
Address Setup Time 0ns
t
AH
Address Hold Time 90 ns
t
DS
Data Setup Time 50 ns
t
DH
Data Hold Time 0ns
t
WP
Write Pulse Width 50 ns
t
WPH
Write Pulse Width High 35 ns
t
WC
Write Cycle Time 85 ns
t
SR/W
Latency between Read and Write Operations 50 ns
t
RP
Reset Pulse Width 500 ns
t
RH
Reset High Time before Read 50 ns
t
EC
Chip Erase Cycle Time 13 seconds
t
SEC1
Sector Erase Cycle Time (4K Word Sectors) 60 90 ms
t
SEC2
Sector Erase Cycle Time (32K Word Sectors) 200 300 ms
t
ES
Erase Suspend Time 15 µs
OE
PROGRAM CYCLE
ADDRESS
A0
55
555
AA
AAA
t
BP
t
WPH
t
WP
CE
WE
A0- A20
DA
TA
t
AS
t
AH
t
WC
t
DH
t
DS
OUTPUT
DATA
555
SR/W
t
VALID
READ ADDRESS
ACC
t
INPUT DATA
18
AT49BV/LV3218(T)
2452F–FLASH–10/02
Sector or Chip Erase Cycle Waveforms
Notes: 1. OE must be high only when WE and CE are both low.
2. For chip erase, the address should be 555. For sector erase, the address depends on what sector is to be erased.
(See note 3 under Command Definitions.)
3. For chip erase, the data should be 10H, and for sector erase, the data should be 30H.
OE
(1)
AA
80
Note 3
55 55
555
555
Note 2
AA
WORD 0
WORD 1 WORD 2
WORD 3
WORD 4
WORD 5
AAA AAA
t
WPH
t
WP
CE
WE
A0 - A20
DATA
t
AS
t
AH
EC
t
t
DH
t
DS
555
t
WC
ADDRESS
VALID
OUTPUT
VALID
ACC
t
t
SR/W
t

AT49BV3218-90CI

Mfr. #:
Manufacturer:
Description:
IC FLASH 32M PARALLEL 48CBGA
Lifecycle:
New from this manufacturer.
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