AT49BV3218-90CI Datasheet AT49BV3218-11TI, AT49BV3218-90TI, AT49BV3218-11CI | P4-P6

AT49BV/LV3218(T)

2452F–FLASH–10/02

Device

Operation

READ: The AT49BV/LV3218(T) is accessed like an EPROM. When CE and OE are low and

is high, the data stored at the memory location determined by the address pins are

asserted on the outputs. The outputs are put in the high-impedance state whenever CE

or OE

is high. This dual-line control gives designers flexibility in preventing bus contention.

COMMAND SEQUENCES: When the device is first powered on it will be reset to the read or

standby mode, depending upon the state of the control line inputs. In order to perform other

device functions, a series of command sequences are entered into the device. The command

sequences are shown in the Command Definitions table (I/O8 - I/O15 are don’t care inputs for

the command codes). The command sequences are written by applying a low pulse on the

or CE input with CE or WE low (respectively) and OE high. The address is latched on the

falling edge of CE

or WE, whichever occurs last. The data is latched by the first rising edge of

or WE. Standard microprocessor write timings are used. The address locations used in the

command sequences are not affected by entering the command sequences.

RESET: A RESET

input pin is provided to ease some system applications. When RESET is at

a logic high level, the device is in its standard operating mode. A low level on the RESET

input

halts the present device operation and puts the outputs of the device in a high-impedance

state. When a high level is reasserted on the RESET

pin, the device returns to the read or

standby mode, depending upon the state of the control inputs.

ERASURE: Before a byte/word can be reprogrammed, it must be erased. The erased state of

memory bits is a logical “1”. The entire device can be erased by using the Chip Erase com-

mand or individual sectors can be erased by using the Sector Erase command.

CHIP ERASE: The entire device can be erased at one time by using the six-byte chip erase

software code. After the chip erase has been initiated, the device will internally time the erase

operation so that no external clocks are required. The maximum time to erase the chip is t

If the sector lockdown has been enabled, the chip erase will not erase the data in the sector

that has been locked out; it will erase only the unprotected sectors. After the chip erase, the

device will return to the read or standby mode.

SECTOR ERASE: As an alternative to a full chip erase, the device is organized into 71 sec-

tors (SA0 - SA70) that can be individually erased. The Sector Erase command is a six-bus

cycle operation. The sector address is latched on the falling WE

edge of the sixth cycle while

the 30H data input command is latched on the rising edge of WE

. The sector erase starts after

the rising edge of WE

of the sixth cycle. The erase operation is internally controlled; it will

automatically time to completion. The maximum time to erase a section is t

SEC

. When the sec-

tor programming lockdown feature is not enabled, the sector will erase (from the same Sector

Erase command). An attempt to erase a sector that has been protected will result in the oper-

ation terminating in 2 µs.

BYTE/WORD PROGRAMMING: Once a memory block is erased, it is programmed (to a logi-

cal “0”) on a byte-by-byte or on a word-by-word basis. Programming is accomplished via the

internal device command register and is a four-bus cycle operation. The device will automati-

cally generate the required internal program pulses.

Any commands written to the chip during the embedded programming cycle will be ignored. If

a hardware reset happens during programming, the data at the location being programmed

will be corrupted. Please note that a data “0” cannot be programmed back to a “1”; only erase

operations can convert “0”s to “1”s. Programming is completed after the specified t

cycle

time. The Data

Polling feature or the Toggle Bit feature may be used to indicate the end of a

program cycle.

AT49BV/LV3218(T)

2452F–FLASH–10/02

SECTOR LOCKDOWN: Each sector has a programming lockdown feature. This feature pre-

vents programming of data in the designated sectors once the feature has been enabled.

These sectors can contain secure code that is used to bring up the system. Enabling the lock-

down feature will allow the boot code to stay in the device while data in the rest of the device is

updated. This feature does not have to be activated; any sector’s usage as a write protected

region is optional to the user.

At power-up or reset all sectors are unlocked. To activate the lockdown for a specific sector,

the six-bus cycle Sector Lockdown command must be issued. Once a sector has been locked

down, the contents of the sector is read-only and cannot be erased or programmed.

SECTOR LOCKDOWN DETECTION: A software method is available to determine if program-

ming of a sector is locked down. When the device is in the software product identification

mode (see Software Product Identification Entry and Exit sections) a read from address loca-

tion 00002H within a sector will show if programming the sector is locked down. If the data on

I/O0 is low, the sector can be programmed; if the data on I/O0 is high, the program lockdown

feature has been enabled and the sector cannot be programmed. The software product identi-

fication exit code should be used to return to standard operation.

SECTOR LOCKDOWN OVERRIDE: The only way to unlock a sector that is locked down is

through reset or power-up cycles. After power-up or reset, the content of a sector that is

locked down can be erased and reprogrammed.

ERASE SUSPEND/ERASE RESUME: TheEraseSuspendcommandallowsthesystemto

interrupt a sector erase operation and then program or read data from a different sector within

the same plane. Since this device has a dual-plane architecture, there is no need to use the

Erase Suspend feature while erasing a sector when you want to read data from a sector in the

other plane. After the Erase Suspend command is given, the device requires a maximum time

of 15 µs to suspend the erase operation. After the erase operation has been suspended, the

plane that contains the suspended sector enters the erase-suspend-read mode. The system

can then read data or program data to any other sector within the device. An address is not

required during the Erase Suspend command. During a sector erase suspend, another sector

cannot be erased. To resume the sector erase operation, the system must write the Erase

Resume command. The Erase Resume command is a one-bus cycle command, which does

require the plane address (determined by A20 - A19). The device also supports an erase sus-

pend during a complete chip erase. While the chip erase is suspended, the user can read from

any sector within the memory that is protected. The command sequence for a chip erase sus-

pend and a sector erase suspend are the same.

PRODUCT IDENTIFICATION: The product identification mode identifies the device and man-

ufacturer as Atmel. It may be accessed by hardware or software operation. The hardware

operation mode can be used by an external programmer to identify the correct programming

algorithm for the Atmel product.

For details, see “Operating Modes” on page 13 (for hardware operation) or “Software Product

Identification Entry/Exit” on page 20. The manufacturer and device codes are the same for

both modes.

128-BIT PROTECTION REGISTER: The device contains a 128-bit register that can be used

for security purposes in system design. The protection register is divided into two 64-bit

blocks. The two blocks are designated as block A and block B. The data in block A is non-

changeable and is programmed at the factory with a unique number. The data in block B is

programmed by the user and can be locked out such that data in the block cannot be repro-

grammed. To program block B in the protection register, the four-bus cycle Program

Protection Register command must be used as shown in the Command Definition table on

page 7. To lock out block B, the four-bus cycle Lock Protection Register command must be

used as shown in the Command Definition table. Data bit D1 must be zero during the fourth

AT49BV/LV3218(T)

2452F–FLASH–10/02

bus cycle. All other data bits during the fourth bus cycle are don’t cares. Please see the “Pro-

tection Register Addressing Table” on page 8 for the address locations in the protection

normal read operation from an address within the protection register. After reading the protec-

tion register, the Product ID Exit command must be given prior to performing any other

operation.

DATA

POLLING: The AT49BV/LV3218(T) features Data Polling to indicate the end of a pro-

gram cycle. During a program cycle an attempted read of the last byte/word loaded will result

in the complement of the loaded data on I/O7. Once the program cycle has been completed,

true data is valid on all outputs and the next cycle may begin. During a chip or sector erase

operation, an attempt to read the device will give a “0” on I/O7. Once the program or erase

cycle has completed, true data will be read from the device. Data

Polling may begin at any

time during the program cycle. Please see “Status Bit Table” on page 21 for more details.

TOGGLE BIT: In addition to Data

Polling, the AT49BV/LV3218(T) provides another method

for determining the end of a program or erase cycle. During a program or erase operation,

successive attempts to read data from the same memory plane will result in I/O6 toggling

between one and zero. Once the program cycle has completed, I/O6 will stop toggling and

valid data will be read. Examining the toggle bit may begin at any time during a program cycle.

An additional toggle bit is available on I/O2, which can be used in conjunction with the toggle

bit that is available on I/O6. While a sector is erase suspended, a read or a program operation

from the suspended sector will result in the I/O2 bit toggling. Please see “Status Bit Table” on

page 21 for more details.

RDY/BUSY

: An open-drain Ready/Busy output pin provides another method of detecting the

end of a program or erase operation. RDY/BUSY

is actively pulled low during the internal pro-

gram and erase cycles and is released at the completion of the cycle. The open-drain

connection allows for OR-tying of several devices to the same RDY/BUSY

line.

HARDWARE DATA PROTECTION: The Hardware Data Protection feature protects against

inadvertent programs to the AT49BV/LV3218(T) in the following ways: (a) V

sense: if V

below 1.8V (typical), the program function is inhibited. (b) V

power-on delay: once V

has

reached the V

sense level, the device will automatically time out 10 ms (typical) before pro-

gramming. (c) Program inhibit: holding any one of OE

low, CE high or WE high inhibits

program cycles. (d) Noise filter: pulses of less than 15 ns (typical) on the WE

or CE inputs will

not initiate a program cycle.

INPUT LEVELS: While operating with a 2.65V to 3.3V power supply, the address inputs and

control inputs (OE

,CEand WE) may be driven from 0 to 5.5V without adversely affecting the

operation of the device. The I/O lines can only be driven from 0 to V

+0.6V.

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P25

AT49BV3218-90CI

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AT49BV3218-90CI

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