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NB6L11MMNG

P1-P3P4-P6P7-P9
© Semiconductor Components Industries, LLC, 2009
August, 2009 − Rev. 4
1 Publication Order Number:
NB6L11M/D
NB6L11M
2.5V / 3.3V 1:2 Differential
CML Fanout Buffer
Multi−Level Inputs w/ Internal Termination
Description
The NB6L11M is a differential 1:2 CML fanout buffer. The
differential inputs incorporate internal 50 W termination resistors that
are accessed through the V
T
pins and will accept LVPECL, LVCMOS,
LVTTL, CML, or LVDS logic levels.
The V
REFAC
pin is an internally generated voltage supply available
to this device only. V
REFAC
is used as a reference voltage for
single−ended PECL or NECL inputs. For all single−ended input
conditions, the unused complementary differential input is connected
to V
REFAC
as a switching reference voltage. V
REFAC
may also rebias
capacitor−coupled inputs. When used, decouple V
REFAC
with a
0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA.
When not used, V
REFAC
output should be left open.
The device is housed in a small 3x3 mm 16 pin QFN package.
The NB6L11M is a member of the ECLinPS MAXt family of
high performance clock products.
Features
• Maximum Input Clock Frequency > 4 GHz, Typical
• 225 ps Typical Propagation Delay
• 70 ps Typical Rise and Fall Times
• 0.5 ps maximum RMS Clock Jitter
• Differential CML Outputs, 380 mV peak−to−peak, typical
• LVPECL Operating Range: V
CC
= 2.375 V to 3.63 V with V
EE
= 0 V
• NECL Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.63 V
• Internal Input Termination Resistors, 50 W
• VREFAC Reference Output
• Functionally Compatible with Existing 2.5 V / 3.3V LVEL, LVEP,
EP, and SG Devices
• −40°C to +85°C Ambient Operating Temperature
• These are Pb−Free Devices
MARKING
DIAGRAM*
http://onsemi.com
QFN−16
MN SUFFIX
CASE 485G
NB6L
11M
ALYWG
G
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G = Pb−Free Package
(Note: Microdot may be in either location)
16
1
*For additional marking information, refer to
Application Note AND8002/D.
See detailed ordering and shipping information in the package
dimensions section on page 8 of this data sheet.
ORDERING INFORMATION
Figure 1. Simplified Logic Diagram
Q0
Q0
Q1
Q1
D
D
VTD
VTD
V
REFAC
NB6L11M
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2
V
CC
V
REFAC
V
EE
V
CC
V
CC
V
EE
V
EE
V
CC
Q0
Q0
Q1
Q1
VTD
D
D
VTD
5678
16 15 14 13
12
11
10
9
1
2
3
4
NB6L11M
Exposed Pad (EP)
Figure 2. Pin Configuration (Top View)
Table 1. PIN DESCRIPTION
Pin Name I/O Description
1 VTD −
Internal 50 W Termination Pin for D input.
2 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Noninverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
3 D ECL, CML,
LVCMOS, LVDS,
LVTTL Input
Inverted Differential Input. Note 1. Internal 50 W Resistor to Termination Pin, VTD.
4 VTD −
Internal 50 W Termination Pin for D input.
5 V
CC
− Positive Supply Voltage
6 V
REFAC
Output Reference Voltage for direct or capacitor coupled inputs
7 V
EE
− Negative Supply Voltage
8 V
CC
− Positive Supply Voltage
9 Q1 CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
.
10 Q1 CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
.
11 Q0 CML Output
Inverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
.
12 Q0 CML Output
Noninverted Differential Output. Typically Terminated with 50 W Resistor to V
CC
.
13 V
CC
− Positive Supply Voltage
14 V
EE
− Negative Supply Voltage
15 V
EE
− Negative Supply Voltage
16 V
CC
− Positive Supply Voltage
− EP − The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the die for
improved heat transfer out of package. The exposed pad must be attached to a heat−sinking
conduit. The pad is not electrically connected to the die, but is recommended to be electrically
and thermally connected to VEE on the PC board.
1. In the differential configuration when the input termination pins (VTD, VTD) are connected to a common termination voltage or left open, and
if no signal is applied on D/D
input, then, the device will be susceptible to self−oscillation.
2. All V
CC
and V
EE
pins must be externally connected to a power supply for proper operation.
NB6L11M
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3
Table 2. ATTRIBUTES
Characteristics Value
ESD Protection Human Body Model
Machine Model
> 2 kV
> 200V
Moisture Sensitivity 16−QFN Level 1
Flammability Rating Oxygen Index: 28 to 34 UL 94 V−0 @ 0.125 in
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
For additional information, see Application Note AND8003/D.
Table 3. MAXIMUM RATINGS
Symbol Parameter Condition 1 Condition 2 Rating Unit
V
CC
Positive Power Supply V
EE
= 0 V 4.0 V
V
EE
Negative Power Supply V
CC
= 0 V −4.0 V
V
IO
Positive Input/Output Voltage
Negative Input/Output Voltage
V
EE
= 0 V
V
CC
= 0 V
−0.5 v V
Io
v V
CC
+ 0.5
+0.5 v V
Io
v V
EE
− 0.5
4.0
−4.0
V
V
V
INPP
Differential Input Voltage |D − D| V
CC
− V
EE
V
I
IN
Input Current Through R
T
(50 W Resistor)
Static
Surge
45
80
mA
mA
I
OUT
Output Current (CML Output) Continuous
Surge
25
50
mA
mA
I
VREFAC
VREFAC Sink/Source Current $0.5 mA
T
A
Operating Temperature Range 16 QFN −40 to +85
_C
T
stg
Storage Temperature Range −65 to +150
_C
q
JA
Thermal Resistance (Junction−to−Ambient)
(Note 3)
0 lfmp
500 lfmp
QFN−16
QFN−16
42
35
_C/W
_C/W
q
JC
Thermal Resistance (Junction−to−Case) (Note 3) QFN−16 4
_C/W
T
sol
Wave Solder Pb−Free 265
_C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
3. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
P1-P3P4-P6P7-P9

NB6L11MMNG

Mfr. #:
Buy NB6L11MMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:2 CML FANOUT
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New from this manufacturer.
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