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NB6L11MMNG

P1-P3P4-P6P7-P9
NB6L11M
http://onsemi.com
4
Table 4. DC CHARACTERISTICS, Multi−Level Inputs V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
= −2.375 V to
−3.63 V, T
A
= −40°C to +85°C
Symbol
Characteristic Min Typ Max Unit
POWER SUPPLY CURRENT
I
CC
Power Supply Current (Inputs and Outputs Open) 45 60 75 mA
CML OUTPUTS (Notes 4 and 5)
V
OH
Output HIGH Voltage
V
CC
= 3.3 V
V
CC
= 2.5 V
V
CC
− 40
3260
2460
V
CC
− 10
3290
2490
V
CC
3300
2500
mV
V
OL
Output LOW Voltage
V
CC
= 3.3V
V
CC
= 2.5V
V
CC
− 500
2800
2000
V
CC
− 400
2900
2100
V
CC
− 300
3000
2200
mV
DIFFERENTIAL INPUT DRIVEN SINGLE−ENDED (see Figures 4 and 5) (Note 6)
V
th
Input Threshold Reference Voltage Range (Note 7) 1125 V
CC
− 75 mV
V
IH
Single−ended Input HIGH Voltage V
th
+ 75 V
CC
mV
V
IL
Single−ended Input LOW Voltage V
EE
V
th
− 75 mV
V
ISE
Single−ended Input Voltage Amplitude (V
IH
− V
IL
) 150 2800 mV
VREFAC
V
REFAC
Output Reference Voltage (V
CC
w 2.5 V) V
CC
– 1525 V
CC
– 1425 V
CC
– 1325 mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY (see Figures 6, 7 and 8) (Note 8)
V
IHD
Differential Input HIGH Voltage V
EE
+ 1200 V
CC
mV
V
ILD
Differential Input LOW Voltage V
EE
V
CC
− 100 mV
V
ID
Differential Input Voltage (V
IHD
− V
ILD
) V
EE
+ 100 V
CC
− V
EE
mV
V
CMR
Input Common Mode Range (Differential Configuration) (Note 9) V
EE
+ 950 V
CC
− 50 mV
I
IH
Input HIGH Current D / D, (VTD/VTD Open) −150 150 uA
I
IL
Input LOW Current D / D, (VTD/VTD Open) −150 150 uA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor 40 50 60
W
R
TOUT
Internal Output Termination Resistor 40 50 60
W
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
4. CML outputs loaded with 50 W to V
CC
for proper operation.
5. Input and output parameters vary 1:1 with V
CC
.
6. V
th
, V
IH
, V
IL,,
and V
ISE
parameters must be complied with simultaneously.
7. V
th
is applied to the complementary input when operating in single−ended mode.
8. V
IHD
, V
ILD,
V
ID
and V
CMR
parameters must be complied with simultaneously.
9. V
CMR
min varies 1:1 with V
EE
, V
CMR
maximum varies 1:1 with V
CC
. The V
CMR
range is referenced to the most positive side of the differential
input signal.
NB6L11M
http://onsemi.com
5
Table 5. AC CHARACTERISTICS V
CC
= 2.375 V to 3.63 V, V
EE
= 0 V, or V
CC
= 0 V, V
EE
= −2.375 V to −3.63 V, T
A
= −40°C to
+85°C; (Note 10)
Symbol
Characteristic Min Typ Max Unit
V
OUTPP
Output Voltage Amplitude (@ V
INPP(MIN)
f
in
≤ 3.0GHz
(Note 15) (See Figure 9) f
in
≤ 3.5 GHz
f
in
≤ 4.0 GHz
230
190
150
380
320
270
mV
t
PD
Propagation Delay D to Q 175 225 325 ps
t
SKEW
Duty Cycle Skew (Note 11)
Within Device Skew
Device to Device Skew (Note 12)
5.0
3.0
15
15
80
ps
t
DC
Output Clock Duty Cycle (Reference Duty Cycle = 50%) f
in
≤ 4.0GHz 40 50 60 %
t
JITTER
RMS Random Clock Jitter (Note 13)
f
in
≤ 4GHz
Peak−to−Peak Data Dependent Jitter
(Note 14) f
in
≤ 4Gb/s
0.2
40
0.5
ps
V
INPP
Input Voltage Swing/Sensitivity
(Differential Configuration) (Note 15)
150 2800 mV
t
r
t
f
Output Rise/Fall Times @ 0.5 GHz Q, Q
(20% − 80%)
70 120 ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
10.Measured by forcing V
INPP
(MIN) from a 50% duty cycle clock source. All loading with an external R
L
= 50 W to V
CC
. Input edge rates 40 ps
(20% − 80%).
11. Duty cycle skew is measured between differential outputs using the deviations of the sum of Tpw− and Tpw+ @ 0.5GHz.
12.Device to device skew is measured between outputs under identical transition @ 0.5 GHz.
13.Additive RMS jitter with 50% duty cycle clock signal.
14.Additive peak−to−peak data dependent jitter with input NRZ data at PRBS23.
15.Input and output voltage swing is a single−ended measurement operating in differential mode.
NB6L11M
http://onsemi.com
6
Figure 3. Input Structure
50 W
50 W
VTD
VTD
V
CC
D
D
R
C
R
C
I
D
V
th
D
V
th
Figure 4. Differential Input Driven
Single−Ended
V
IH
V
IL
V
IHmax
V
ILmax
V
IH
V
th
V
IL
V
IHmin
V
ILmin
V
CC
V
thmax
V
thmin
V
EE
V
th
Figure 5. V
th
Diagram
D
D
Figure 6. Differential Inputs
Driven Differentially
V
ILD(MAX)
V
IHD(MAX)
V
IHD
V
ILD
V
IHD(MIN)
V
IL(MIN)
V
CMR
GND
V
ID
= V
IHD
− V
ILD
V
CC
D
D
Q
Q
t
PD
t
PD
V
OUTPP
= V
OH
(Q) − V
OL
(Q)
V
INPP
= V
IH
(D) − V
IL
(D)
Figure 7. Differential Inputs Driven Differentially
Figure 8. V
CMR
Diagram Figure 9. AC Reference Measurement
V
IHD
V
ILD
V
ID
= |V
IHD(D)
− V
ILD(D)|
D
D
P1-P3P4-P6P7-P9

NB6L11MMNG

Mfr. #:
Buy NB6L11MMNG
Manufacturer:
ON Semiconductor
Description:
Clock Buffer 1:2 CML FANOUT
Lifecycle:
New from this manufacturer.
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