DS8007-ENG+ Datasheet DS8007-ENG+, DS8007-KIT | P25-P27

DS8007

Hardware Status Register (HSR)

R = unrestricted read, W = unrestricted write, -n = value after reset, x = always reflects state of external device pin. This register is

reset to 0uuuxxxub on RIU = 0.

Note: A minimum of 2µs is needed between successive reads of the HSR to allow for hardware updates. In addition, a minimum of

2µs is needed between reads of the HSR and activation of card A, card B, or the AUX card.

76543210

Address 0Fh — PRTLB PRTLA SUPL PRLB PRLA INTAUXL PTL

R-0 R-0 R-0 R-1 R-0 R-0 R-0 R-0

Bit 7: Reserved.

Bit 6: Protection Card Interface B Status Bit

(PRTLB). This bit is set to 1 when a fault has been

detected on card reader interface B. A fault is defined

as detection of a short-circuit condition on either the

RSTB or V

CCB

pin as given by DC specs I

RST(SD)

and

CC(SD)

. The INT signal is asserted at logic 0 (active)

while this bit is set. This bit returns to 0 after any HSR

read, unless the condition persists.

Bit 5: Protection Card Interface A Status Bit

(PRTLA). This bit is set to a 1 when a fault has been

detected on card reader interface A. A fault is defined

as detection of a short-circuit condition on either the

RSTA or V

CCA

pin as given by DC specs I

RST(SD)

and

CC(SD).

The INT signal is asserted at logic 0 (active)

while this bit is set. This bit returns to 0 after any HSR

read, unless the condition persists.

Bit 4: Supervisor Latch (SUPL). This bit is set to 1

when V

< V

RST

or when a reset is caused by exter-

nally driving the DELAY pin < 1.25V. At this time the

INT signal is asserted at logic 0 (active). This bit returns

to 0 only after an HSR read outside the alarm pulse.

Bit 3: Presence Latch B (PRLB). This bit is set to 1

when a level change has been detected on the PRESB

pin of card interface B. The INT signal is asserted at

logic 0 (active) while this bit is set. This bit returns to 0

after any HSR read.

Bit 2: Presence Latch A (PRLA). This bit is set to 1

when a level change has been detected on the PRESA

pin of card interface A. The INT signal is asserted at

logic 0 (active) while this bit is set. This bit returns to 0

after any HSR read.

Bit 1: INTAUX Latch (INTAUXL). This bit is set to 1

when a 0 → 1 or a 1 → 0 level change has been detect-

ed on the INTAUX pin. This bit remains set, regardless

of further level changes on the INTAUX pin until cleared

to 0 by any HSR read.

Bit 0: Protection Thermal Latch (PTL). This bit is set

to 1 when excessive heating (approximately +150°C or

greater) is detected. The INT signal is asserted at logic

0 (active) while this bit is set. This bit returns to 0 after

any HSR read, unless the condition persists.

Multiprotocol Dual Smart Card Interface

______________________________________________________________________________________ 25

DS8007

Multiprotocol Dual Smart Card Interface

26 ______________________________________________________________________________________

Card Interface Voltage Regulation

and Step-Up Converter Operation

The V

and V

DDA

pins supply power to the DS8007.

Voltage supervisor circuitry detects the input voltage

levels and automatically engages a step-up converter if

necessary to generate the appropriate voltages to the

card interfaces according to the control register set-

tings. The conversion process is transparent to the user

and is usually only noticed by changes in the V

voltage, which reflects the operation of the internal

charge pump. Table 2 elaborates on the V

pin.

The V

and V

DDA

pins must be decoupled externally,

but extra care must be taken to decouple large current

spikes that can occur on the V

DDA

pins because of

noise generated by the cards and internal voltage step-

up circuitry.

Voltage Supply Supervision

The voltage supervisor circuitry monitors V

and

holds the device in reset until V

is at a satisfactory

level. The DELAY pin is an external indicator of the

state of internal power and can also be driven external-

ly to hold the device in a reset state. An external capac-

itor is usually attached to this pin, defining the time

constant of a power-on delay for the DS8007. When

is below the voltage threshold V

RST

, the charging

path that exists between V

and DELAY is discon-

nected and a strong pulldown is enabled on the DELAY

pin. Once V

exceeds V

RST

, the strong pulldown on

the DELAY pin is released and the pullup to V

enabled, allowing the external DELAY capacitor to be

charged.

The RSTOUT alarm pin is released (allowing it to be

pulled up externally) whenever the DELAY pin voltage

is less than V

DRST

, whether caused by V

< V

RST

as a result of external hardware pulling the DELAY pin

low. The minimum duration of the RSTOUT pulse (t

specification) is defined by the capacitor connected to

the DELAY pin and is typically 1ms per 2nF. The

RSTOUT pin is driven strongly low once the DELAY pin

exceeds the V

DRST

voltage threshold.

The SUPL bit is set on initial power-up and is reset

again when the RSTOUT alarm pulse occurs. The SUPL

bit may only be cleared by a read of the HSR register.

Figure 8 illustrates the sequencing of the various sig-

nals involved.

Short-circuit and thermal-protection circuitry prevent

damages done by accidentally shorting the V

CCx

pins

or when the ambient temperature is exceeding the

maximum operating temperature. When the internal

temperature is approximately +150°C, the voltage V

CCx

and the drivers to the CLKx, RSTx, I/Ox, C4x, and C8x

signals to both card interfaces are turned off. The PTL

bit in the HSR is set and an interrupt is generated.

When a short is detected on the RSTx pin, the device

initiates a normal deactivation sequence. A short on

I/Ox, C4x, and C8x does not cause deactivation.

VOLTAGE (V)

DDA

SMART CARD V

< 2.4 X V

DDA

2.4–3.5 5 5.7

3.5–5.5 5 5.7

5.5–6.0 5 V

DDA

2.4–3.5 3.0 4.1

> 3.5 3.0 V

DDA

2.4–6.0 1.8 V

DDA

Table 2. Step-Up Converter Operation

DS8007

DELAY

RSTOUT

INT

SUPL BIT

RST

= 2.1V TO 2.5V

DRST

= ~1.25V

RESULTING FROM

< V

RST

DELAY DRIVEN

LOW EXTERNALLY

SUPL BIT CLEARED BY HSR READ ONLY

Figure 8. Voltage Supervisor

Multiprotocol Dual Smart Card Interface

______________________________________________________________________________________ 27

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18 P19-P21 P22-P24 P25-P27 P28-P30 P31-P33 P34-P36 P37-P39 P40-P41

DS8007-ENG+

Mfr. #:

Buy DS8007-ENG+

Manufacturer:

Maxim Integrated

Description:

Interface - Specialized Multiprotocol Dual Smart Card Interface

Lifecycle:

New from this manufacturer.

Delivery:

DHL FedEx Ups TNT EMS

Payment:

T/T Paypal Visa MoneyGram Western Union

DS8007-ENG+

DS8007-ENG+

Products related to this Datasheet