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DS8007-ENG+

P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41
Last Character to Transmit
The ISO UART implements a special control input that
allows an automatic switch from transmit mode
(UCR1.T/R = 1) to receive mode (UCR1.T/R = 0) upon
successful character transmission. The last character
to transmit (UCR1.LCT) bit must be set to 1 by host
software prior to writing the last character for transmis-
sion to UTR. Upon successful transmission of the char-
acter, the UCR1.T/R bit and the LCT bit are cleared by
hardware. When the LCT bit is used, the TBE/RBF bit is
not set at the end of the transmission.
Receive Mode
The ISO UART receive mode is in effect if the associat-
ed UCR1.T/R bit is 0. When the ISO UART is changed
to receive mode, the MSR.FE bit is set to 1 to indicate
that the receive FIFO is empty. When at least one
unread receive character exists in the FIFO, the FE bit
is cleared. When the FIFO, with depth defined by
FL2–FL0, is full, the TBE/RBF bit is set to 1 to indicate
that the receive buffer is full. Once a character is read
from a full FIFO, the RBF/TBE bit is cleared to indicate
that the FIFO is no longer full. The controller ready
(CRED) bit should be polled to assess data readiness
when reading from register URR at high frequencies.
Parity Check
The T = 1 protocol selection checks receive parity. For
T = 1, the parity error count bits (PEC2–PEC0) have no
function and the USR.PE bit are set on the first parity
error.
The T = 0 protocol selection also checks receive parity,
but allows setting of the USR.PE parity error bit to be
based upon detection of 1–8 parity errors. The
PEC2–PEC0 bits define the number of consecutive par-
ity errors that should be detected before setting
USR.PE.
The ISO UART implements a special control input that
allows testing for inverse parity. If the UCR1.FIP bit is
configured to 0 during receive mode, the ISO UART
tests for correct parity on each received character. If
UCR1.FIP is configured to 1, inverse parity is expected.
This control can be useful in testing that the ICC prop-
erly detects error signals generated by the DS8007 and
retransmits requested characters.
DS8007
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________ 37
LCT BIT WRITTEN TO 1 BY
SOFTWARE, THEN LOAD UTR.
LAST CHARACTER TO TRANSMIT
TBE REMAINS 0, LCT AND
T/R BITS ARE BOTH CLEARED
TO 0 BY HARDWARE.
PLAST CHARACTER
LAST CHARACTER
I/O
TBE/RBF BIT
LCT BIT
T/R BIT
P
Figure 15. Last Character to Transmit
DS8007
Error-Signal Generation
The T = 1 protocol does not support error-signal gener-
ation. When configured to receive using the T = 0 pro-
tocol (UCR1.PROT = 0), the DS8007 supports error-
signal generation in response to parity. The parity error
count bits (PEC2–PEC0) of the FIFO control register
(FCR) determine the number of allowed repetitions in
reception, and therefore the number of times that an
error signal is generated in response to a received
character with incorrect parity before the USR.PE bit
becomes set.
When receiving a character, the DS8007 verifies even
parity for the combination of the received 8-bit charac-
ter and parity bit. If incorrect parity is determined and
consecutive parity error counter has not reached termi-
nal count (000b), the DS8007 generates an error signal
on the I/Ox line starting at 10.5 ETU and lasting for 1.0
ETU. The parity error counter is initialized through the
PEC2–PEC0 bits. Configuring the PEC2–PEC0 bits to
000b means that no repetition in reception is allowed
and that an error signal generation occurs in response
to a character received with incorrect parity.
Configuring PEC2–PEC0 bits to 001b means one repe-
tition in reception is allowed and that the DS8007 gen-
erates an error signal only once per character receive
attempt. When the consecutive parity error counter
reaches 000b and a character is received with
incorrect parity, the USR.PE bit is set to 1. If the parity
error counter has not reached terminal count, it is reset
to the originally programmed value upon reception of a
character having the correct parity. Once the USR.PE
bit signals a parity count error, the software must re-
establish any nonzero PEC2–PEC0 setting.
Receive FIFO
The DS8007 implements an enhanced receive FIFO. If
the FIFO threshold-enable bits FTE0 and FTE1 are set
to 0, the FIFO functions as a standard FIFO that is con-
figurable to a depth of 1 to 8 characters. The T = 0 and
T = 1 protocols allow the FIFO depth to be determined
by the FCR.FL2–FCR.FL0 bits. When configurable, the
FIFO depth is equal to (FL2–FL0) + 1 (e.g., FL2–FL0 =
001b configures the FIFO depth to 2). The RBF/TBE
and FE status bits report the full and empty FIFO condi-
tions, respectively. If the receive FIFO is full (at a maxi-
mum depth of 8), the FIFO Overrun (OVR) bit is set to 1,
the new character received is lost, and the previous
FIFO contents remain undisturbed.
The received characters are read from the URR. When
the receive FIFO is enabled, reads of the URR always
access the oldest available received data. The FIFO is
initialized every time the receive mode is invoked (i.e.,
T/R bit is cleared to 0).
Multiprotocol Dual Smart Card Interface
38 ______________________________________________________________________________________
CHARACTER N
ERROR-SIGNAL GENERATION (T = 0 PROTOCOL ONLY)
PARITY BIT DOES NOT CHECK
IF (INCORRECT PARITY AND PEC ≠ 000b)
HARDWARE ERROR SIGNAL IS GENERATED
BETWEEN 10.5 ETU AND 11.5 ETU
AND DECREMENT PARITY COUNTER.
IF (CORRECT PARITY AND PE = 0)
RESET PARITY ERROR COUNTER TO
ORIGINAL PEC2–PEC0
PROGRAMMED VALUE.
ETU TIME => 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
P
P
CHARACTER N (RETRANSMIT)
Figure 16. Receive Mode—Error Signal Generation
For the T = 0 protocol, only received characters without
parity errors are stored in the receive FIFO. When
UCR1.FIP = 1 during T = 0 reception, only those char-
acters with incorrect parity are stored to the receive
FIFO since the DS8007 is checking for inverse parity.
For the T = 1 protocol, the receive character is stored
to the FIFO no matter whether the parity checks cor-
rectly or not.
If the FIFO threshold enable bits FTE0 and FTE1 are set
to 1, the FIFO implements a programmable threshold
for the assertion of the RBF/TBE bits and the interrupt
line. In this mode, the internal FIFO length is forced to 8
bytes, and FL[2:0] (the programmable FIFO length bits)
determines the threshold value.
Characters are accumulated in the FIFO without setting
the RBF/TBE bits until the FIFO depth is greater than
the threshold value. As long as the used depth is
greater than the FL[2:0] value, the RBF/TBE bits (USR
and MSR) are set and the interrupt pin is asserted.
Reading the FIFO to a level less than or equal to the
threshold value resets the RBF/TBE bit and deasserts
the interrupt line.
Writing a zero or eight into the FL bits while the pro-
grammable threshold mode is enabled causes the
FIFO to behave as it does in nonprogrammable thresh-
old mode.
If the programmable FIFO depth is at its maximum (8
characters), the RBF/TBE bit is set when the eighth
character is received and written into the FIFO. If anoth-
er character is received while the FIFO is full, the over-
flow (OVR) status is set, and the new character
overwrites the previously received character.
If the programmable FIFO depth is set to zero, the
receipt of a single character sets RBF/TBE. Receiving
another character in this state sets the OVR bit and
overwrites the character.
The FIFO empty status bit (FE) operates as before. The
programmable threshold feature functions the same in
T = 0 and T = 1 modes.
Early Answer (EA)
If a start bit is detected on the I/O line during the ATR
between clock cycles 200–368 when the RSTx pin is
low and during the first 368 clock cycles after the RSTx
is high, it is recognized as an early answer (EA), and
the EA bit is set in the USR.EA register. When the EA bit
is set, INT is asserted.
During the early answer detection period, 46 clock
cycles sampling periods should be used to detect the
start bit and there is an undetected (uncertainty) period
of 32 clock cycles at the end for both cases (between
clock cycles 200–368 when the RSTx pin is low, and
the first 368 clock cycles after RSTx is high). Table 6
summarizes the status of the early answer bit. The
answer on the I/O line begins between 400 and 40,000
clock cycles after the rising edge of the RSTx signal.
Development and Technical
Support
The DS8007 evaluation kit (EV kit) is available to assist
in the development of designs using the DS8007 multi-
protocol smart card interface. The EV kit can be pur-
chased directly from Maxim.
For technical support, go to https://support.maxim-
ic.com/micro.
DS8007
Multiprotocol Dual Smart Card Interface
______________________________________________________________________________________ 39
Table 6. Early Answer Detection
WHEN START BIT
IS ASSERTED
EA BIT
STATUS
CHARACTER
RECEIVED
Between 0 and 200 clock
cycles when RSTx = low
0 No
Between 200 and 368 clock
cycles when RSTx = low
1 Yes
Between 368 and 400 clock
cycles when RSTx = low
0 Yes
Within the first 368 clock
cycles after RSTx = high
1 Yes
Between 368 and 400 clock
cycles after RSTx = high
0 Yes
Package Information
For the latest package outline information and land patterns (footprints), go to www.maxim-ic.com/packages. Note that a “+”, “#”, or
“-” in the package code indicates RoHS status only. Package drawings may show a different suffix character, but the drawing pertains
to the package regardless of RoHS status.
PACKAGE TYPE PACKAGE CODE OUTLINE NO. LAND PATTERN NO.
48 LQFP C48+2
21-0054 90-0093
P1-P3P4-P6P7-P9P10-P12P13-P15P16-P18P19-P21P22-P24P25-P27P28-P30P31-P33P34-P36P37-P39P40-P41

DS8007-ENG+

Mfr. #:
Buy DS8007-ENG+
Manufacturer:
Maxim Integrated
Description:
Interface - Specialized Multiprotocol Dual Smart Card Interface
Lifecycle:
New from this manufacturer.
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