DS8007-ENG+ Datasheet DS8007-ENG+, DS8007-KIT | P34-P36

DS8007

Multiprotocol Dual Smart Card Interface

34 ______________________________________________________________________________________

parameters continue to be used until a successful PPS

exchange is completed. The negotiated Fn, Dn values

are then used after a successful PPS exchange. If the

card comes up in specific mode (i.e., TA(2) is present

in ATR), then the indicated Fi, Di values apply immedi-

ately after successful ATR if bit 5 of the TA(2) charac-

ter is 0. If bit 5 of TA(2) is 1, implicit values should be

used. The TA(1) character of ATR, if present, contains

the Fi and Di values indicated by the card.

Table 5 demonstrates how the prescaler (PSC) bit and

programmable divider register (PDRx) can be config-

ured to generate the requested F/D ratios. All settings

assume that the CKU bit is configured to its reset

default logic 0 state.

Table 4. Fi, Di Parameter Possibilities

TA(1).Fi Fi MAX CLKx (MHz) Fi = TA(1).Di Di

0000 372 4 31 x 12 0000 RFU

0001 372 5 31 x 12 0001 1

0010 558 6 31 x 18 0010 2

0011 744 8 31 x 24 0011 4

0100 1116 12 31 x 36 0100 8

0101 1488 16 31 x 48 0101 16

0110 1860 20 31 x 60 0110 32

0111 RFU — — 0111 RFU

1000 RFU — — 1000 RFU

1001 512 5 32 x 16 1001 12

1010 768 7.5 32 x 24 1010 20

1011 1024 10 32 x 32 1011 RFU

1100 1536 15 32 x 48 1100 RFU

1101 2048 20 32 x 64 1101 RFU

1110 RFU RFU — 1110 RFU

1111 RFU RFU — 1111 RFU

RFU = Reserved for future use.

Table 5. PSC, PDR Settings to Support F, D Parameters

PDR SETTING FOR Di =

TA(1).Fi

PSC

0 = /31

1 = /32

0001 0010 0011 0100 0101 0110 1000 1001

0000 0 12 6 3 — — — 1 —

0001 0 12 6 3 — — — 1 —

0010 0 18 9 — — — — — —

0011 0 24 12 6 3 — — 2 —

0100 0 36 18 9 — — — 3 —

0101 0 48 24 12 6 3 — 4 —

0110 0 60 30 15 — — — 53

1001 1 16 8 4 2 1 — — —

1010 1 24 12 6 3 — — 2 —

1011 1 32 16 8 4 2 1 — —

1100 1 48 24 12 6 3 — 4 —

1101 1 64 32 16 8 4 2 — —

Character Encoding/

Decoding Convention

The ISO UART is designed to support two possible char-

acter encoding/decoding formats: direct and inverted.

The direct character coding convention transmits and

receives data LSb first and associates a high logic level

with a bit 1 and a low logic level with a bit 0. The inverse

character coding convention transmits and receives data

most significant bit first and associates a high logic level

with a bit 0 and a low logic level with a bit 1.

The UCR1.CONV bit defines which character conven-

tion (CONV = 0:inverse; CONV = 1:direct) should be

used by the ISO UART. The UCR1.CONV bit can be

configured by the host device software or be config-

ured by hardware if automatic convention detection has

been enabled.

Automatic Convention Detection

The automatic convention detection relies upon recog-

nition of a predefined pattern in the first character

received (TS character) in ATR for establishing future

character coding convention. To enable automatic con-

vention detection, the UCR1.SS bit must be set to logic

1 and the UCR2.AUTOC bit should be configured to

logic 0 prior to ATR. The SS bit is automatically cleared

by hardware 10.5 ETU after the character is received. If

automatic convention detection is enabled and an

unrecognized character is received, the CONV bit is

not written. If neither the direct nor inverse character

are detected, a parity error occurs along with error sig-

nal generation for the T = 0 protocol. The AUTOC bit

should not be modified during a card session.

Framing Error Detection

The DS8007 monitors the selected card I/Ox signal at

10.25 ETU following each detected start bit. If the I/Ox

signal is not in the high state at this point in time, the

USR.FER (framing error) bit is set to 1 at 10.5 ETU. The

FER bit is cleared to 0 whenever USR is read.

DS8007

Multiprotocol Dual Smart Card Interface

______________________________________________________________________________________ 35

TS CHARACTER

(CONVEYS CODING CONVENTION)

DIRECT CONVENTION (BYTE = 3Bh)

INVERSE CONVENTION (BYTE = 3Fh)

LSb

MSb

LSb

Figure 12. Direct, Inverse Character Coding Conventions

ISO UART

URR

I/OA

I/OB

I/OAUX

CLKx

2 x f

CLKx

START DETECT

ETU

FIFO(8)

UTR

PDR.PD[7:0]

GTR.GTR.[7:0]

UCR1

UCR2

CSR.RIU

MSR.FE

MSR.BGT

MSR.TBE/RBF

USR.EA

FCR.PEC[2:0]

FCR.FL[2:0]

USR.PE

USR.OVR

USR.FER

Figure 13. ISO UART Signal Interface

DS8007

Block Guard Time

The block guard time for the asynchronous serial com-

munication between the smart card reader (DS8007)

and the ICC is defined as the minimum delay between

consecutive start bits sent in the opposite direction.

The DS8007 implements an internal ETU counter

specifically to help the host device assess that this min-

imum block guard time is being met. This internal ETU

counter is loaded on each start bit with the value 22d or

16d, dependent upon the protocol selected. For T = 0,

the counter is loaded with the value 16d and for T = 1,

the counter is loaded with the value 22d. If the counter

reaches 0, the MSR.BGT status bit is set and the

counter stops. If a start bit is detected before the

counter reaches 0, the counter is reloaded and the

BGT status bit is cleared to 0.

Transmit Mode

The ISO UART transmit mode is invoked by setting the

associated UCR1.T/R bit to logic 1. When the ISO

UART is placed into transmit mode, the TBE/RBF bit is

set to 1 to indicate that the transmit buffer is empty.

When a character is written to UTR register, the

TBE/RBF bit is cleared to indicate that the transmit

buffer is no longer empty. If the transmit serial shift reg-

ister is available (which is the case unless character

retransmission is occurring), the character is translated

according to the character coding convention (CONV

bit) and moved from the transmit buffer to the serial

shift register. The TBE/RBF bit returns high so that

another character can be loaded into the UTR register.

Guard Time

Some smart cards require extra time to handle informa-

tion received from an interface device. To allow this

extra time, the DS8007 implements a Guard Time

grammed with the number of extra ETU that should be

enforced between consecutive start bits transmitted by

the DS8007 (discounting retransmissions at the request

of the ICC). The GTR register defaults to 00h on reset,

indicating that no extra guard time is required (i.e., 12

ETU must be enforced between transmission of con-

secutive start bits). If the GTR register is programmed

to FFh, the delay required between consecutive start

bits is dependent upon the protocol selected (per

UCR1.PROT).

GTR = FFh

T = 0 protocol: 11.8 ETU

T = 1 protocol: 10.8 ETU

Multiprotocol Dual Smart Card Interface

36 ______________________________________________________________________________________

BLOCK GUARD TIME (BGT) COUNTER AND STATUS

BGT COUNTER ≠ 0:

- CLEAR BGT BIT

- RESTART BGT COUNTER

(e.g., 16 ETU FOR T = 0)

BGT COUNTER = 0 (STOPPED):

SET BGT BIT

BGT BIT

I/Ox

Figure 14. Block Guard Time ETU Counter Operation

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DS8007-ENG+

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Interface - Specialized Multiprotocol Dual Smart Card Interface

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