HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 22 November 2011 10 of 19
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (C
L
in pF).
[2] In the divide-by-n mode (PL connected to TC), the CP0 or CP
1 pulse width must be greater than the maximum HIGH to LOW
propagation delay for CP0 or CP
1 to TC.
t
W
pulse width CP0 input; LOW;
see Figure 6
5 V 8040- ns
10 V 40 20 - ns
15 V 30 15 - ns
CP
1 input; HIGH;
see Figure 6
5 V 8040- ns
10 V 40 20 - ns
15 V 30 15 - ns
PL input; HIGH;
see Figure 6
5 V 100 50 - ns
10 V 40 20 - ns
15 V 32 16 - ns
MR input; LOW 5 V 130 65 - ns
10 V 50 25 - ns
15 V 40 20 - ns
f
max
maximum frequency PL = LOW;
see Figure 6
5 V
[2]
612- MHz
10 V 1225- MHz
15 V 1632- MHz
Table 9. Dynamic characteristics
…continued
V
SS
= 0 V; T
amb
= 25
C; for test circuit see Figure 7; unless otherwise specified.
Symbol Parameter Conditions V
DD
Extrapolation formula Min Typ Max Unit
Table 10. Dynamic power dissipation P
D
P
D
can be calculated from the formulas shown. V
SS
= 0 V; t
r
= t
f
20 ns; T
amb
= 25
C.
Symbol Parameter V
DD
Typical formula for P
D
(W) where:
P
D
dynamic power
dissipation
5 V P
D
= 1000 f
i
+ (f
o
C
L
) V
DD
2
f
i
= input frequency in MHz,
f
o
= output frequency in MHz,
C
L
= output load capacitance in pF,
V
DD
= supply voltage in V,
(f
o
C
L
) = sum of the outputs.
10 V P
D
= 4000 f
i
+ (f
o
C
L
) V
DD
2
15 V P
D
= 10000 f
i
+ (f
o
C
L
) V
DD
2
