HEF4526B All information provided in this document is subject to legal disclaimers. © NXP B.V. 2011. All rights reserved.
Product data sheet Rev. 5 — 22 November 2011 4 of 19
NXP Semiconductors
HEF4526B
Programmable 4-bit binary down counter
5. Pinning information
5.1 Pinning
5.2 Pin description
Fig 4. Pin configuration
HEF4526B
Q3 V
DD
A3 Q2
PL A2
CP1 CF
A0 TC
CP0 A1
Q0 MR
V
SS
Q1
001aae720
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
Table 2. Pin description
Symbol Pin Description
A0 to A3 5, 11, 14, 2 parallel input
PL 3 parallel load input
CP0 6 clock input (LOW-to-HIGH, triggered)
CP
1 4 clock input (HIGH-to-LOW, triggered)
CF 13 cascade feedback input
MR 10 asynchronous master reset input
TC 12 terminal count output
Q0 to Q3 7, 9, 15, 1 buffered parallel output
V
DD
16 supply voltage
V
SS
8 ground (0 V)
