Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
16
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PCB Layout
Switcher
The board layout has a significant impact on the performance of
the device. It is important to isolate high current ground returns,
in order to minimize ground bounce that could produce reference
errors in the device. The method used to isolate power ground
from noise sensitive circuitry is a star ground. This approach
makes sure the high current components such as the input capaci-
tor, output capacitor, and diode have very low impedance paths
to each other. Figure 5 illustrates the technique. The ground from
each of the components should be very close to each other and
be connected on the same surface as the components. Internal
ground planes should not be used for the star ground connec-
tion, because vias add impedance to the current path. In order to
further reduce noise effects on the PCB, noise sensitive traces
should not be connected to internal ground planes.
The feedback network from the switcher output should have an
independent ground trace that goes directly to the exposed pad
underneath the device. The exposed pad should be connected to
internal ground planes and to any exposed copper used for heat
dissipation. If the grounds from the device also are connected
directly to the exposed pad, the ground reference from the feed-
back network will be less susceptible to noise injection or ground
bounce.
To reduce radiated emissions from the high frequency switching
nodes it is important to have an internal ground plane directly
under the LX node. The plane should not be broken directly
under the switching path because the lowest impedance path for
radiated emissions is back to the star ground using the ground
plane directly under the signal trace. If another trace does break
the return path, the energy will have to find another path, which
is through radiated emissions or through stray eddy currents.
Motor Driver
In order to use PWM current control, a low-value resistor is
placed between the LSSx pin and ground for current sensing
purposes. To minimize ground-trace IR drops in sensing the
output current level, the current sensing resistor should have an
independent ground return to the star ground point. This trace
should be as short as possible. For low-value sense resistors, the
IR drops in the PCB can be significant, and should be taken into
account. When selecting a value for the sense resistor be sure not
to exceed the maximum voltage on the SENSEx pin of ±500 mV
at maximum load. During overcurrent events, this rating may be
exceeded for short durations.
Thermal Considerations
The PCB should have a thick ground plane. For optimum
electrical and thermal performance, the A3998 must be soldered
directly onto the board. On the underside of the A3998 package is
an exposed pad, which provides a path for enhanced thermal dis-
sipation. The thermal pad must be soldered directly to an exposed
surface on the PCB in order to achieve optimal thermal conduc-
tion. Thermal vias are used to transfer heat to other layers of the
PCB. The load supply pin, VBB, should be decoupled with an
electrolytic capacitor (typically 100 F) in parallel with a lower
valued ceramic capacitor placed as close as practicable to the
device
Switching Regulator Component Selection
External component recommended values are provided in table 3.
V
OUT1
The regulator requires an external clamping diode, D1,
inductor, L1, and filter capacitor, COUT1 (see figure 1).
The output voltage is determined by an external resistive voltage
divider, according to the following formula:
V
OUT1
= V
FB1
× (1 + R1 / R2) (5)
Application Information
Star Ground
Current path (on-cycle )
Current path (off-cycle )
C
IN
L
Q1
D
C
OUT
R
LOAD
Figure 5. Star Ground Connection
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
17
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
PAD
A3998
GND
PMON
RSTN
VREF
FB1
FB2
GD/VOUT2
VIN
OUT2B
VBB
OUT2A
SENSE2
GND
SENSE1
OUT1A
VBB
CSN
VREG
NC
VCP
CP2
CP1
SW1
OUT1B
GND
FRST
SLEEPN
CLK
DATA
STB
ENB1
ENB2
L1
D1
VBB
CVBB1
CVBB2
RS2 RS1
VOUT2
COUT2
CVREG
CCP
CVCP
RCL2
R2
Q1
R1
R4
R3
VOUT1
OUT1BOUT2B OUT1AOUT2A
COUT1
GND
PCB Layout Diagram
PCB
Thermal Vias
Trace (2 oz.)
Signal (1 oz.)
Ground (1 oz.)
Thermal (2 oz.)
Solder
A3998
R1
R2
VOUT2
COUT2
Q1
L1
D1
CVBB2
RS1
RS2
RCL2
CVREG
CVCP
CCP
CVBB1
COUT1
GND
GND
GND
GND
GND
OUT2B
OUT2A
OUT1A OUT1B
VBB
R4
VOUT1
R3
U1
Dual DMOS Full Bridge Motor Driver
With Serial Port Control and Dual Regulators
A3998
18
Allegro MicroSystems, LLC
115 Northeast Cutoff
Worcester, Massachusetts 01615-0036 U.S.A.
1.508.853.5000; www.allegromicro.com
The total resistance from V
OUT1
to FB1 to GND should be less
than 10 k.
D1 The Schottky catch diode should be rated to handle 1.2 times
the maximum load current. The voltage rating should be higher
than the maximum input voltage expected during any operating
condition. The duty cycle for high input voltages can be very
close to 100%.
L1 The inductor must be rated to handle the total load current
and the value chosen must keep the ripple current to a reasonable
value. The ripple current, I
R
, can be calculated by:
I
R
= V
L(OFF)
× (t
OFF
/ L) (6)
where
V
L(OFF)
= V
OUT1
+ V
f
+ I
av
× R
L
(7)
The switching frequency can then be estimated by:
f
PWM
= 1 / ( t
ON
+ t
OFF
) (8)
where
t
ON
= I
R
× L / V
L(ON)
(9)
and
V
L(ON)
= V
BB
I
av
× R
DS(on)
I
av
× R
L
– V
OUT1
(10)
Higher inductor values can be chosen to lower the ripple cur-
rent. This may be an option if it is required to increase the total
maximum current available that can be drawn from the switching
regulator. The maximum total current available is:
I
LOAD(max)
= I
CL
(min) – I
R
/ 2 (11)
Where I
CL
(min) is from the Electrical Characteristics table.
COUT1 The output capacitor main consideration is voltage ripple
on the output. For electrolytic output capacitors, a low ESR type
is recommended. The peak to peak output ripple is simply:
I
R(pp)
= I
R
× ESR (12)
Note that the ripple current can be decreased by increasing the
inductor value. The minimum voltage rating of the capacitor is
10 V, however, because ESR decreases with voltage, the most
cost effective choice may be a higher rated voltage.
V
OUT2
This output requires a 10 F ceramic output capacitor,
COUT2.
Table 3. Recommended Components
Configuration Component
Output f
PWM
Symbol Description Representative Component
V
OUT1x
5 V / 1 A 220 kHz
L1 68 H 3BSumida RCH1216BNP-680K
COUT1 220 F / 25 V, ESR = 72 m Rubycon ZL 25ZL220M8x11.5
D1 60 V / 3 A Schottky diode NSQ03A06
R1 2 k
R2 499
3.3V/1A 230 kHz
L1 68 H 4BSumida RCH1216BNP-680K
COUT1 220 F / 25 V, ESR = 72 m Rubycon ZL 25ZL220M8x11.5
D1 60 V / 3 A Schottky diode Vishay SS36
R1 2 k
R2 866
V
OUT2x
Q1 External MOSFET - C
gs
< 1000 pF
RSx Sense resistor
COUT2 10 F /10 V X5R
R3, R4

A3998SETTR-T

Mfr. #:
Manufacturer:
Description:
IC MTR DRVR BIPOLAR 3-5.5V 32QFN
Lifecycle:
New from this manufacturer.
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