MAX1135BEAP+T Datasheet MAX1135BCAP+, MAX1135BEAP+, MAX1135BEAP+T | P10-P12

MAX1134/MAX1135

The user-programmable outputs are set to zero during

power-on reset or when RST goes low. During hardware

or software shutdown, P0, P1, and P2 are unchanged

and remain low impedance.

Starting a Conversion

Start a conversion by clocking a control byte into the

device’s internal shift register. With CS low, each rising

edge on SCLK clocks a bit from DIN into the

MAX1134/MAX1135s’ internal shift register. After CS

goes low or after a conversion or calibration completes,

the first arriving logic 1 is defined as the start bit of the

control byte. Until this first start bit arrives, any number of

logic 0 bits can be clocked into DIN with no effect. If at

any time during acquisition or conversion CS is brought

high and then low again, the part is placed into a state

where it can recognize a new start bit. If a new start bit

occurs before the current conversion is complete, the

conversion is aborted and a new acquisition is initiated.

Internal and External Clock Modes

The MAX1134/MAX1135 use either the external serial

clock or the internal clock to perform the successive-

approximation conversion. In both clock modes, the

external clock shifts data in and out of the

MAX1134/MAX1135. Bit 5 (INT/EXT) of the control byte

programs the clock mode.

External Clock

In external clock mode, the external clock not only

shifts data in and out, but also drives the ADC conver-

sion steps.

In short acquisition mode, SSTRB pulses high for one

clock period after the seventh falling edge of SCLK fol-

lowing the start bit. The MSB of the conversion is avail-

able at DOUT on the eighth falling edge of SCLK

(Figure 2).

16-Bit ADCs, 150ksps, 3.3V Single Supply

10 ______________________________________________________________________________________

SCLK

DOUT

A/D

STATE

DIN

SSTRB

418

START

M1 M0

P1 P0

UNI/

BIP

INT/

EXT

14 29 32

B4B14

B15

MSB

B13

LSB

FILLED WITH

ZEROS

ACQ

ACQUISITION CONVERSIONIDLE IDLE

Figure 3. Long Acquisition Mode (32 Clock Cycles) External Clock

SDV

SSTRB

STR

P1 CLOCKED IN

SSTRB

SCLK

Figure 4. External Clock Mode SSTRB Detailed Timing

MAX1134/MAX1135

16-Bit ADCs, 150ksps, 3.3V Single Supply

______________________________________________________________________________________ 11

SCLK

DOUT

DIN

SSTRB

418

START

M1 M0

P1 P0

UNI/

BIP

INT/

EXT

9 21 24

B14

B15

MSB

LSB

FILLED WITH

ZEROS

ACQ

CONV

B13

Figure 5. Internal Clock Mode Timing, Short Acquisition

In long acquisition mode, when using external clock,

SSTRB pulses high for one clock period after the 15th

falling edge of SCLK following the start bit. The MSB of

the conversion is available at DOUT on the 16th falling

edge of SCLK (Figure 3).

In external clock mode, SSTRB is high impedance when

CS is high (Figure 4). CS is normally held low during the

entire conversion. If CS goes high during the conver-

sion, SCLK is ignored until CS goes low. This allows

external clock mode to be used with 8-bit bytes.

Internal Clock

In internal clock mode, the MAX1134/MAX1135 gener-

ate their own conversion clock. This frees the micro-

processor from the burden of running the SAR

conversion clock, and allows the conversion results to

be read back at the processor’s convenience, at any

clock rate up to 4MHz.

SSTRB goes low at the start of the conversion and goes

high when the conversion is complete. SSTRB is low for

a maximum of 7µs, during which time SCLK should

remain low for best noise performance. An internal reg-

ister stores data when the conversion is in progress.

SCLK clocks the data out of the internal storage regis-

ter at any time after the conversion is complete.

The MSB of the conversion is available at DOUT when

SSTRB goes high. The subsequent 15 falling edges on

SCLK shift the remaining bits out of the internal storage

once a conversion is started.

When internal clock mode is selected, SSTRB does not

go into a high-impedance state when CS goes high.

Figure 6 shows the SSTRB timing in internal clock

mode. In internal clock mode, data can be shifted into

the MAX1134/MAX1135 at clock rates up to 4MHz, pro-

P0 CLOCKED IN

SSTRB

CONV

SCK

CSS

SSTRB

SCLK

NOTE: FOR BEST NOISE PERFORMANCE, KEEP SCLK LOW DURING CONVERSION.

CSH

Figure 6. Internal Clock Mode SSTRB Detailed Timing

MAX1134/MAX1135

vided the minimum acquisition time, t

ACQ

, is kept

above 1.39µs in bipolar mode and 1.67µs in unipolar

mode. Data can be clocked out at 4MHz.

Output Data

The output data format is straight binary for unipolar

conversions and two’s complement in bipolar mode.

The MSB is shifted out of the MAX1134/MAX1135 first

in both modes.

Data Framing

The falling edge of CS does not start a conversion on the

MAX1134/MAX1135. The first logic high clocked into

DIN is interpreted as a start bit and defines the first bit of

the control byte. A conversion starts on the falling edge

of SCLK, after the seventh bit of the control byte (the P1

bit) is clocked into DIN. The start bit is defined as:

• The first high bit clocked into DIN with CS low any-

time the converter is idle, e.g., after AV

applied.

• The first high bit clocked into DIN after CS is pulsed

high then low.

If a falling edge on CS forces a start bit before the con-

version or calibration is complete, then the current

operation terminates and a new one starts.

Applications Information

Power-On Reset

When power is first applied to the MAX1134/MAX1135,

or if RST is pulsed low, the internal calibration registers

are set to their default values. The user-programmable

registers (P0, P1, and P2) are low, and the device is

configured for bipolar mode with internal clocking.

Calibration

Periodically calibrate the MAX1134/MAX1135 to com-

pensate for temperature drift and other variations. After

any change in ambient temperature of more than

+10°C, the device should be recalibrated. A 100mV

change in supply voltage or any change in the refer-

ence voltage should be followed by a calibration.

Calibration corrects for errors in gain, offset, integral

nonlinearity, and differential nonlinearity.

The MAX1134/MAX1135 should be calibrated after

power-up or after the assertion of reset. Make sure the

power supplies and the reference voltage have fully

settled prior to initiating the calibration sequence.

Initiate calibration by setting M1 = 0 and M0 = 1 in the

control byte. In internal clock mode, SSTRB goes low at

the beginning of calibration and goes high to signal the

end of calibration, approximately 80,000 clock cycles

later. In external clock mode, SSTRB goes high at the

beginning of calibration and goes low to signal the end

of calibration. Calibration should be performed in the

same clock mode that is used for conversions.

Reference

The MAX1134/MAX1135 require a 2.048V reference.

The reference must be bypassed with a 4.7µF capaci-

tor. The input impedance at REF is a minimum of 16kΩ

for DC currents. During conversion, the external refer-

ence at REF must deliver up to 150µA DC load current

and have an output impedance of 10Ω or less.

Analog Input

The MAX1134/MAX1135 use a capacitive DAC that

provides an inherent track/hold function. Drive AIN with

a source impedance less than 10Ω. Any signal condi-

tioning circuitry must settle with 16-bit accuracy in less

than 500ns. Limit the input bandwidth to less than half

the sampling frequency to eliminate aliasing. The

MAX1134/MAX1135 have a complex input impedance

that varies from unipolar to bipolar mode (Figure 1).

Input Range

The analog input range in unipolar mode is 0 to +6V for

the MAX1134, and 0 to +2.048V for the MAX1135. In

bipolar mode, the analog input can be -6V to +6V for

the MAX1134, or -2.048V to +2.048V for the MAX1135.

Unipolar or bipolar mode is programmed with the

UNI/BIP bit of the control byte. When using a reference

other than the suggested 2.048V, the full-scale input

range varies accordingly. The full-scale input range

depends on the voltage at REF and the sampling mode

selected (Tables 3 and 4).

16-Bit ADCs, 150ksps, 3.3V Single Supply

12 ______________________________________________________________________________________

PART ZERO SCALE FULL SCALE

MAX1134 0 +6 (V

REF

/2.048)

MAX1135 0 +V

REF

PART

NEGATIVE FULL

SCALE

ZERO

SCALE

FULL SCALE

MAX1134 -6 (V

REF

/2.048) 0 +6 (V

REF

/2.048)

MAX1135 -V

REF

0+V

REF

Table 3. Unipolar Full Scale and Zero

Scale

Table 4. Bipolar Full Scale, Zero Scale,

and Negative Full Scale

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1135BEAP+T

Mfr. #:

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Manufacturer:

Maxim Integrated

Description:

Analog to Digital Converters - ADC 16-Bit 150ksps 3.3V Single Supply

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MAX1135BEAP+T

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