MAX1135BEAP+T Datasheet MAX1135BCAP+, MAX1135BEAP+, MAX1135BEAP+T | P7-P9

MAX1134/MAX1135

16-Bit ADCs, 150ksps, 3.3V Single Supply

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Pin Description

PIN NAME FUNCTION

1 REF ADC Reference Input. Connect a 2.048V voltage source to REF. Bypass REF to AGND with a 4.7µF capacitor.

2AV

Analog Supply. Connect to pin 4.

3 AGND Analog Ground. This is the primary analog ground (star ground).

4AV

Analog Supply, 3.3V ±5%. Bypass AV

to AGND (pin 3) with a 0.1µF capacitor.

5 DGND Digital Ground

6 SHDN Shutdown Control Input. Drive SHDN low to put the ADC in shutdown mode.

7 P2 User-Programmable Output 2

8 P1 User-Programmable Output 1

9 P0 User-Programmable Output 0

10 SSTRB

Serial Strobe Output. In internal clock mode, SSTRB goes low when the ADC begins a conversion and goes

high when the conversion is finished. In external clock mode, SSTRB pulses high for one clock period before

the MSB decision. It is high impedance when CS is high in external clock mode.

11 DOUT

Serial Data Output. MSB first, straight binary format for unipolar input, two’s complement for bipolar input.

Each bit is clocked out of DOUT at the falling edge of SCLK.

12 RST Reset Input. Drive RST low to put the device in the power-on default mode. See the Power-On Reset section.

13 SCLK

Serial Data Clock Input. Serial data on DIN is loaded on the rising edge of SCLK, and serial data is updated

on DOUT on the falling edge of SCLK. In external clock mode, SCLK sets the conversion speed.

14 DGND Digital Ground. Connect to pin 5.

15 DV

Digital Supply, 3.3V ±5%. Bypass DV

to DGND (pin 14) with a 0.1µF capacitor.

16 DIN Serial Data Input. Serial data on DIN is latched on the rising edge of SCLK.

17 CS

Chip-Select Input. Drive CS low to enable the serial interface. When CS is high, DOUT is high impedance. In

external clock mode, SSTRB is high impedance when CS is high.

18 CREF Reference Buffer Bypass. Bypass CREF to AGND (pin 3) with a 1µF capacitor.

19 AGND Analog Ground. Connect to pin 3.

20 AIN Analog Input

MAX1134/MAX1135

Detailed Description

The MAX1134/MAX1135 ADCs use a successive-

approximation technique and input track/hold (T/H) cir-

cuitry to convert an analog signal to a 16-bit digital

output. The MAX1134/MAX1135 easily interface to

microprocessors (µPs). The data bits can be read either

during the conversion in external clock mode or after the

conversion in internal clock mode.

In addition to a 16-bit ADC, the MAX1134/MAX1135

include an input scaler, an internal digital microcontroller,

calibration circuitry, and an internal clock generator.

The input scaler for the MAX1134 enables conversion

of input signals ranging from 0 to +6V (unipolar input)

or ±6V (bipolar input). The MAX1135 accepts 0 to

+2.048V (unipolar input) or ±2.048V (bipolar input). The

input range is software selectable.

Calibration

To minimize linearity, offset, and gain errors, the

MAX1134/MAX1135 have on-demand software calibra-

tion. Initiate calibration by writing a control byte with bit

M1 = 0 and bit M0 = 1 (Table 1). Select internal or exter-

nal clock for calibration by setting the INT/EXT bit in the

control byte. Calibrate the MAX1134/MAX1135 with the

same clock mode used for performing conversions.

Offsets resulting from synchronous noise (such as the

conversion clock) are canceled by the MAX1134/

MAX1135’s calibration circuitry. However, because the

magnitude of the offset produced by a synchronous

signal depends on the signal’s shape, recalibration

may be appropriate if the shape or relative timing of the

clock, or other digital signals change, as may occur if

more than one clock signal or frequency is used.

Input Scaler

The MAX1134/MAX1135 have an input scaler, which

allows conversion of true bipolar input voltages while

operating from a single 3.3V supply. The input scaler

attenuates and shifts the input as necessary to map the

external input range to the input range of the internal

ADC. The MAX1134 analog input range is 0 to +6V

(unipolar) or ±6V (bipolar). The MAX1135 analog input

16-Bit ADCs, 150ksps, 3.3V Single Supply

8 _______________________________________________________________________________________

BIT NAME DESCRIPTION

7 (MSB) START The first logic 1 bit after CS goes low defines the beginning of the control byte.

6 UNI/BIP

1 = unipolar, 0 = bipolar. Selects unipolar or bipolar conversion mode. In unipolar mode, analog input

signals from 0 to +6V (MAX1134) or 0 to +V

REF

(MAX1135) can be converted. In bipolar mode, analog

input signals from -6V to +6V (MAX1134) or -V

REF

to +V

REF

(MAX1135) can be converted.

5 INT/EXT Selects the internal or external conversion clock. 1 = internal, 0 = external.

M1 M0 Mode

0 0 24 external clocks per conversion (short acquisition mode)4M1

0 1 Start calibration: starts internal calibration

1 0 Software power-down mode

3M0

1 1 32 external clocks per conversion (long acquisition mode)

2P2

1P1

0 (LSB) P0

These 3 bits are stored in a port register and output to pins P2, P1, and P0 for use in addressing a mux

or PGA. These 3 bits are updated in the port register simultaneously when a new control byte is written.

Table 1. Control Byte Format

VOLTAGE

REFERENCE

BIPOLAR

UNIPOLAR

TRACK

S1 = BIPOLAR/UNIPOLAR

S2, S3 = T/H SWITCH

R2 = 7.6kΩ (MAX1134)

OR 2.5kΩ (MAX1135)

R3 = 3.9kΩ (MAX1134)

OR INFINITY (MAX1135)

HOLD

T/H OUT

HOLD

32pF

2.5kΩ

AIN

TRACK

Figure 1. Equivalent Input Circuit

range is 0 to +2.048V (unipolar) or ±2.048V (bipolar).

Unipolar and bipolar mode selection is configured with

bit 6 of the serial control byte (Table 1).

Figure 1 shows the equivalent input circuit of the

MAX1134/MAX1135. The resistor network on the analog

input provides ±16.5V fault protection. This circuit limits

the current going into or out of the pin to less than 2mA.

The overvoltage protection is active even if the device

is in a power-down mode, or if AV

= 0.

Digital Interface

The digital interface pins consist of SHDN, RST,

SSTRB, DOUT, SCLK, DIN, and CS. Bringing SHDN low

places the MAX1134/MAX1135 in its 1.2µA shutdown

mode. A logic low on RST halts the MAX1134/MAX1135

operation and returns the part to its power-on-reset

state.

In external clock mode, SSTRB is low and pulses high

for one clock cycle at the start of conversion. In internal

clock mode, SSTRB goes low at the start of the conver-

sion, and goes high to indicate that the conversion is

finished.

The DIN input accepts control byte data, which is

clocked in on each rising edge of SCLK. After CS goes

low or after a conversion or calibration completes, the

first logic 1 clocked into DIN is interpreted as the

START bit, the MSB of the 8-bit control byte.

The SCLK input is the serial-data-transfer clock, which

clocks data in and out of the MAX1134/MAX1135.

SCLK also drives the ADC conversion steps in external

clock mode (see the Internal and External Clock Modes

section).

DOUT is the serial output of the conversion result.

DOUT is updated on the falling edge of SCLK. DOUT is

high impedance when CS is high.

CS must be low for the MAX1134/MAX1135 to accept a

control byte. The serial interface is disabled when CS is

high.

User-Programmable Outputs

The MAX1134/MAX1135 have three user-program-

mable outputs: P0, P1, and P2. The power-on default

state for the programmable outputs is zero. These are

push-pull CMOS outputs suitable for driving a multi-

plexer, a PGA, or other signal preconditioning circuitry.

Bits 0, 1, and 2 of the control byte control the user-pro-

grammable outputs (Tables 1, 2).

MAX1134/MAX1135

16-Bit ADCs, 150ksps, 3.3V Single Supply

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ACQUISITION CONVERSIONIDLE IDLE

SCLK

DOUT

A/D

STATE

DIN

SSTRB

41812

START

M1 M0

P1 P0

UNI/

BIP

INT/

EXT

15 21 24

B12 B11B14 B13

B10

B9 B4

B15

MSB

FILLED WITH

ZEROS

B3 B1

LSB

ACQ

Figure 2. Short Acquisition Mode (24 Clock Cycles) External Clock

OUTPUT PIN

PROGRAMMED

THROUGH CONTROL

BYTE

POWER-ON OR

RST DEFAULT

DESCRIPTION

P2 Bit 2 0

P1 Bit 1 0

P0 Bit 0 0

User-programmable outputs follow the state of the control

byte’s 3 LSBs, and are updated simultaneously when a new

control byte is written. Outputs are push-pull. In hardware and

software shutdown, these outputs are unchanged and remain

low impedance.

Table 2. User-Programmable Outputs

P1-P3 P4-P6 P7-P9 P10-P12 P13-P15 P16-P18

MAX1135BEAP+T

Mfr. #:

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Analog to Digital Converters - ADC 16-Bit 150ksps 3.3V Single Supply

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