MAX1134/MAX1135
16-Bit ADCs, 150ksps, 3.3V Single Supply
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TIMING CHARACTERISTICS (Figures 5 and 6) (continued)
(AV
DD
= DV
DD
= 3.3V ±5%, T
A
= T
MIN
to T
MAX
, unless otherwise noted.)
Note 1: Tested at AV
DD
= DV
DD
= 3.3V, bipolar input mode.
Note 2: Relative accuracy is the deviation of the analog value at any code from its theoretical value after the gain error and offset
error have been nullified.
Note 3: Offset nullified.
Note 4: Conversion time is defined as the number of clock cycles multiplied by the clock period; clock has 50% duty cycle. Includes
the acquisition time.
Note 5: Acquisition time is 5 clock cycles in short acquisition mode and 13 clock cycles in long acquisition mode.
Note 6: Performance is limited by the converter’s noise floor, typically 300µV
P-P
.
Note 7: When an external reference has a different voltage than the specified typical value, the full scale of the ADC scales propor-
tionally.
Note 8: Defined as the change in positive full scale caused by a ±5% variation in the nominal supply voltage.
Typical Operating Characteristics
(MAX1134/MAX1135, AV
DD
= DV
DD
= 3.3V, f
SCLK
= 3.6MHz, external clock (50% duty cycle), 24 clocks/conversion (150ksps),
bipolar input, REF = 2.048V, 4.7µF on REF, 1µF on CREF, T
A
= +25°C, unless otherwise noted.)
