CY25404ZXI012 Datasheet CY25404ZXI009, CY25404ZXI011T, CY25404ZXI012T | P1-P3

CY25404

Quad PLL Programmable Clock Generator

with Spread Spectrum

Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600

Document #: 001-43258 Rev. *E Revised December 3, 2014

Features

■ Four fully integrated phase-locked loops (PLLs)

■ Input frequency range

❐ External crystal: 8 to 48 MHz

❐ External reference: 8 to 166 MHz clock

■ Wide operating output frequency range

❐ 3 to 166 MHz

■ Programmable spread spectrum with center and down

spread option and lexmark and linear modulation profiles

■ Selectable V

supply voltage options:

❐ 2.5 V, 3.0 V, and 3.3 V

■ Selectable output clock voltages, independent of V

supply:

❐ 1.8 V, 2.5 V, 3.0 V, and 3.3 V

■ Frequency select feature with option to select eight different

frequencies over nine clock outputs

■ Output enable, and SS ON/OFF controls

■ Low jitter, high accuracy outputs

■ Ability to synthesize nonstandard frequencies with

Fractional-N capability

■ Up to nine clock outputs with programmable drive strength

■ Glitch-free outputs while frequency switching

■ 20-pin TSSOP package

■ Commercial and Industrial temperature ranges

Benefits

■ Multiple high performance PLLs allow synthesis of unrelated

frequencies

■ Nonvolatile programming for personalization of PLL

frequencies, spread spectrum characteristics, drive strength,

crystal load capacitance, and output frequencies

■ Application specific programmable electromagnetic

interference (EMI) reduction using spread spectrum for

clocks

■ Programmable PLLs for system frequency margin tests

■ Meets critical timing requirements in complex system

designs

■ Suitability for PC, consumer, portable, and networking

applications

■ Capable of zero parts per million (PPM) frequency synthesis

error

■ Uninterrupted system operation during clock frequency

switch

■ Application compatibility in standard and low power systems

For a complete list of related documentation, click here.

OSC

PLL1

PLL2

PLL3

(SS)

PLL4

(SS)

Output

Dividers

and

Drive

Strength

Control

CLK1

CLK9

CLK8

CLK7

CLK6

CLK5

CLK4

CLK3

CLK2

FS 2

FS 1

FS 0

SSON

XOUT

XIN/

EXCLKIN

Bank

MUX

and

Control

Logic

Crossbar

Switch

Block Diagram

CY25404

Document #: 001-43258 Rev. *E Page 2 of 13

Contents

General Description .........................................................4

Four Configurable PLLs ..............................................4

Input Reference Clocks ...............................................4

Power Supply Options .........................................4

Output Bank Settings ..................................................4

Output Source Selection .............................................4

Spread Spectrum Control ............................................4

Frequency Select ........................................................4

Glitch-Free Frequency Switch .....................................4

Output Enable Mode ...................................................4

Output Drive Strength ..................................................4

Generic Configuration and Custom Frequency ...........4

Absolute Maximum Conditions....................................... 5

Recommended Operating Conditions ............................5

DC Electrical Specifications ............................................6

Recommended Crystal Specification

for SMD Package ..............................................................7

Recommended Crystal Specification

for Thru-Hole Package .....................................................7

AC Electrical Specifications ............................................7

Test and Measurement Setup ..........................................8

Voltage and Timing Definitions .......................................8

Ordering Information ........................................................9

Possible Configurations ...............................................9

Ordering Code Definitions ...........................................9

Package Drawing and Dimensions ...............................10

Acronyms ........................................................................11

Document Conventions .................................................11

Units of Measure .......................................................11

Document History Page .................................................12

Sales, Solutions, and Legal Information ......................13

Worldwide Sales and Design Support ....................... 13

Products ....................................................................13

PSoC Solutions .........................................................13

CY25404

Document #: 001-43258 Rev. *E Page 3 of 13

Figure 1. Pin Diagram - CY25404 20 LD TSSOP

Table 1. Pin Definition - CY25404 (V

= 2.5 V, 3.0 V or 3.3 V Supply)

Pin Number Name IO Description

Power Power supply: 2.5 V/3.0 V/3.3 V

2 XOUT Output Crystal output

3 XIN/EXCLKIN Input Crystal Input or 1.8 V external clock input

Power Power supply ground

5 CLK1 Output Programmable clock output. Output voltage depends on V

_CLK_B1 voltage

_CLK_B1 Power Power supply for Bank1, (CLK1, CLK2, CLK3) outputs: 1.8 V/2.5 V/3.0 V/3.3 V

7 CLK2 Output Programmable clock output. Output voltage depends on V

_CLK_B1 voltage

Power Power supply ground

9 CLK3/FS0 Output/Input Multifunction programmable pin: Programmable clock output or frequency select

input pin. Output voltage of CLK3 depends on V

_CLK_B1 voltage

10 OE/FS1 Input Multifunction programmable pin: High-true output enable or frequency select pin

11 CLK4/FS2 Output/Input Multifunction programmable pin: Programmable clock output or frequency select

input pin. Output voltage of CLK4 depends on V

_CLK_B2 Voltage

12 CLK5 Output Programmable clock output. Output voltage depends on V

_CLK_B2 voltage

13 V

Power Power supply ground

14 CLK6 Output Programmable clock output. Output voltage depends on V

_CLK_B2 voltage

15 V

_CLK_B2 Power Power supply for Bank2, (CLK4, CLK5, CLK6) outputs: 1.8 V/2.5 V/3.0 V/3.3 V

16 CLK7/SSON Output/Input Multifunction programmable pin. Programmable clock output or spread spectrum

On/OFF control input pin. Output voltage of CLK7 depends on V

_CLK_B3

voltage

17 V

_CLK_B3 Power Power supply for Bank3, (CLK7, CLK8, CLK9) outputs: 1.8 V/2.5 V/3.0 V/3.3 V

18 CLK8 Output Programmable clock output. Output voltage depends on V

_CLK_B3 voltage

19 V

Power Power supply ground

20 CLK9 Output Programmable clock output. Output voltage depends on V

_CLK_B3 voltage

VDD

XOUT

XIN/EXCLKIN

VSS

CLK1

VDD_CLK_B1

CLK2

VSS

CLK3/FS0

OE/FS1

CLK5

CLK6

VSS

CLK7/SSON

VDD_CLK_B2

VDD_CLK_B3

CLK9

VSS

CLK4/FS2

CY25404

CLK8

P1-P3 P4-P6 P7-P9 P10-P12 P13-P13

CY25404ZXI012

Mfr. #:

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Manufacturer:

Cypress Semiconductor

Description:

Clock Generators & Support Products PREMIS SSCG EMI Reduction

Lifecycle:

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CY25404ZXI012

CY25404ZXI012

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