NCP1280
http://onsemi.com
15
Maximum Duty Cycle
A dedicated internal comparator limits the maximum ON
time of OUT1 by comparing the FF Ramp to V
DC(inv)
. If the
FF Ramp voltage exceeds V
DC(inv)
, the output of the Max
DC Comparator goes high.
This will reset the Output Latch,
thus turning OFF the outputs and limiting the duty cycle.
Duty cycle is defined as:
DC +
t
on
T
+ t
on
f
Therefore, the maximum ON time can be set to yield the
desired DC if the operating frequency is known. The
maximum ON time is set by adjusting the FF Ramp to reach
V
DC(inv)
in a time equal to t
on(max)
as shown in Figure 33.
The maximum ON time should be set for the minimum line
voltage. As line voltage increases, the slope of the FF Ramp
increases. This reduces the duty cycle below DC
MAX
, which
is a desirable feature as the duty cycle is inversely
proportional to line voltage.
Figure 33. Maximum ON Time Limit Waveforms
Oscillator Ramp
0 V
0 V
FF Ramp
T
t
on(max)
V
DC(inv)
2 V
An internal resistor divider from a 2.0 V reference is used
to set V
DC(inv)
. If the DC
MAX
pin is grounded, V
DC(inv)
is
0.88 V. If the pin is floating, V
DC(inv)
is 1.19 V. This is
equivalent to 60% or 80% of a 1.5 V FF Ramp. V
DC(inv)
can
be adjusted to other values by using an external resistor
network on the DC
MAX
pin. For example, if the minimum
line voltage is 100 V, R
FF
is 1.82 M, operating frequency
is 200 kHz and a maximum duty cycle of 70% is required,
V
DC(inv)
is calculated as follows:
V
DC(inv)
+
I
FF
6.7 k t
on(max)
C
FF
125 k
V
DC(inv)
+
55.2 A 6.7 k 3.5 s
10 pF 125 k
+1.04 V
This can be achieved by connecting a 19.6 k resistor
from the DC
MAX
pin to GND. The maximum duty cycle
limit can be disabled connecting a 100 k resistor between
the DC
MAX
and V
REF
pins.
5.0 V Reference
The NCP1280 includes a precision 5.0 V reference output.
The reference output is biased directly from V
AUX
and it can
supply up to 6 mA. Load regulation is 50 mV and line
regulation is 100 mV over the complete operating range.
It is recommended to bypass the reference output with a
0.1 F ceramic capacitor. The reference output is disabled
when an UV fault is present.
PWM Comparator
In steady state operation, the PWM comparator adjusts the
duty cycle by comparing the error signal to the FF Ramp.
The error signal is fed into the V
EA
input. The V
EA
input can
be driven directly with an optocoupler and a pullup resistor
from V
REF
. The drive of the V
EA
pin is simplified by
internally incorporating a series diode and resistor. The
series diode provides a 0.7 V offset between V
EA
input and
the PWM comparator inverting input. The outputs are
enabled if the V
EA
voltage is approximately 0.7 above the
valley voltage of the FF Ramp.
The pullup resistor is selected such that in the absence of
the error signal, the voltage on the V
EA
pin exceeds the peak
amplitude of the FF Ramp. Otherwise, the converter will not
be able to reach maximum duty cycle. The V
EA
range
required to control the DC from 0% to DC
MAX
is given by
the equation below:
V
EA(L)
t V
EA
t
ǒ
I
FF DC
186.56 pf f
) V
EA(L)
Ǔ
where, V
EA(L)
is the PWM comparator lower input
threshold.
Soft−Start
Soft−start (SS) allows the converter to gradually reach
steady state operation, thus reducing startup stress and
surges on the system. The duty cycle is limited during a
soft−start sequence by comparing the Oscillator Ramp to the
SS voltage (V
SS
) by means of the Soft−Start Comparator.
A 6.2 A current source starts to charge the capacitor on
the SS pin once faults are removed and V
AUX
reaches 11 V.
The Soft−Start Comparator controls the duty cycle while the
SS voltage is below 2.0 V. Once V
SS
reaches 2.0 V, it exceeds
the Oscillator Ramp voltage and the Soft−Start Comparator
does not limit the duty cycle. Figure 34 shows the
relationship between the outputs duty cycle and the
soft−start voltage.
